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STLC5464 multi-hdlc with n x 64 switching matrix associated may 1997 pqfp160 (plastic quad flat pack) order code : STLC5464 . 32 txhdlcs with broadcasting capa- bility and/or csma/cr function with automatic restart in case of tx frame abort . 32 rxhdlcs including address rec- ognition . 16 command/indicate channels (4 or 6-bit primitive) . 16 monitor channels processed in accordance with gci or v* . 256 x 256 switching matrix without blocking and with time slot se- quence integrity and loopback per bidirectional connection . dma controller for 32 tx channels and 32 rx channels . hdlcs and dma controller are capa- ble of handling a mix of lapd, lapb, ss7, cas and proprietary signallings . external shared memory access be- tween dma controller and micro- processor . single memory shared between nx multi-hdlc s and single micro- processor allows to handle n x 32 channels . bus arbitration . interface for various 8,16 or 32 bit microprocessors . ram controller allows to inter- face up to : -16 megabytes of dynamic ram or -1 megabyte of static ram . interrupt controller to store automatically events in shared memory . pqfp160 package description the STLC5464 is a subscriber line interface card controller for central office, central exchange, nt2 and pbx capable of handling : - 16 u interfaces or - 2 megabits line interface cards or - 16 slics (plain old telephone service) or - mixed analogue and digital interfaces (slics or u interfaces) or - 16 s interfaces - switching network with centralized processing 1/83
contents page i pin information .................................................... 8 i.1 pin connections . . . . . . . . . . . . . . . . . . . . . . ............................. 8 i.2 pin description . . . . ................................................ 9 i.3 pin definition . . . . . . . . . . . . . . . . . . . . . . . . . . . ........................... 13 i.3.1 input pin definition . .................................................... 13 i.3.2 output pin definition . . . . . . . . . . . . . . . . . . . . . . ............................. 13 i.3.3 input/output pin definition . .............................................. 13 ii block diagram .................................................... 14 iii functional description ........................................... 15 iii.1 the switching matrix n x 64 kbits/s . . . . . . . . . ......................... 15 iii.1.1 function description . . . . . . . . . . . . . . . . . . . . . . ............................. 15 iii.1.2 architecture of the matrix . . . . . . . . . . . . . . . . . . . . . . . ......................... 15 iii.1.3 connection function . . . . . . . . . . . . . . . . . . . . . . ............................. 15 iii.1.4 loop back function . . . . ................................................ 15 iii.1.5 delay through the matrix . . . . . . . . . . . . . . . . . . . . . . . ......................... 17 iii.1.5.1 variable delay mode . . . . ............................................. 17 iii.1.5.2 sequence integrity mode . . . . .......................................... 17 iii.1.6 connection memory . . . . ................................................ 21 iii.1.6.1 description . . . . . . . . . . . . . . . . . . . . . . . . ................................. 21 iii.1.6.2 access to connection memory . . . . . . . . . . . . .............................. 21 iii.1.6.3 access to data memory . .............................................. 21 iii.2 hdlc controller . ................................................. 21 iii.2.1 function description . . . . ................................................ 21 iii.2.1.1 format of the hdlc frame . ........................................... 21 iii.2.1.2 composition of an hdlc frame . . . . .................................... 21 iii.2.1.3 description and functions of the hdlc bytes . . . . . . . . . . . . . . . . . . . . . . . ....... 23 iii.2.2 csma/cr capability . . . . . . . . . . . . . . . . . . . . . . ............................. 23 iii.2.3 time slot assigner memory . . . . .......................................... 24 iii.2.4 data storage structure . . . . ............................................. 24 iii.2.4.1 reception . . . . ...................................................... 24 iii.2.4.2 transmission . . . . ................................................... 24 iii.2.4.3 frame relay . ....................................................... 24 iii.2.5 transparent modes . . . . ................................................ 26 iii.2.6 command of the hdlc channels . ........................................ 26 iii.2.6.1 reception control . . . . ................................................ 26 iii.2.6.2 transmission control . . . . ............................................. 26 iii.3 c/i and monitor . . . . ................................................ 26 iii.3.1 function description . . . . . . . . . . . . . . . . . . . . . . ............................. 26 iii.3.2 gci and v* protocol . . . . ................................................ 27 iii.3.3 structure of the treatment . .............................................. 27 iii.3.4 ci and monitor channel configuration . ..................................... 27 iii.3.5 ci and monitor transmission/reception command . . . . . . . . . . . . . . . . . . . . . . . .... 27 iii.4 microprocessor interface . . . . .................................... 28 iii.4.1 description . .......................................................... 28 iii.4.2 definition of the interface for the different microprocessors . . . . . . . . . ............. 28 STLC5464 2/83
iii.5 memory interface . . . . ............................................. 31 iii.5.1 function description . . . . . . . . . . . . . . . . . . . . . . ............................. 31 iii.5.2 choice of memory versus microprocessor and capacity required . . . . . . ........... 31 iii.5.3 memory cycle . ....................................................... 31 iii.5.4 sram interface . . . . ................................................... 32 iii.5.4.1 18k x n sram . . . . . . . . . . . . . . . . . . . . . . . . . . . ........................... 32 iii.5.4.2 512k x n sram . .................................................... 32 iii.5.5 dram interface . . . . ................................................... 32 iii.5.5.1 256k x n dram . .................................................... 32 iii.5.5.2 1m x n dram . . . . ................................................... 33 iii.5.5.3 4m x n dram . . . . ................................................... 33 iii.6 bus arbitration . . . . ................................................ 33 iii.7 clock selection and time synchronization . . . . . . . . . . . . . . . . . . . . . . . . 34 iii.7.1 clock distribution selection and supervision . . . . . . . . . . . . . . . . . . . . . . . .......... 34 iii.7.2 vcxo frequency synchronization . ........................................ 34 iii.8 interrupt controller . . . . . . . . . . . . . . . . . . . . . . . ...................... 35 iii.8.1 description . .......................................................... 35 iii.8.2 operating interrupts (int0 pin) . . . . ....................................... 35 iii.8.3 time base interrupts (int1 pin) . . . . . . . . . . . . .............................. 35 iii.8.4 emergency interrupts (wdo pin) . . ........................................ 35 iii.8.5 interrupt queues . . . . . . . . . . . . . . . . . . . . . . . . . . . ........................... 35 iii.9 watchdog . . . . . . . . . . . . . . . . . . . . . . . . ................................. 36 iii.10 reset . . . . . . ...................................................... .. 36 iv dc specifications .................................................. 37 v clock timing ....................................................... 38 v.1 synchronization signals delivered by the system . . . . . . ........... 38 v.2 tdm synchronization . . . . .......................................... 39 v.3 gci interface . . . . . . . . . . . . . . . . . . . . . . . . . . . ........................... 40 v.4 v* interface . . . . ................................................... 41 vi memory timing ..................................................... 42 vi.1 dynamic memories . . . . ............................................. 42 vi.2 static memories . . . . . . . . . . . . . . . . . . . . . . ............................. 44 vii microprocessor timing ............................................ 46 vii.1 st9 family mod0=1, mod1=0, mod2=0 . . . . . . . . . . . . . . . . . . . . . . . .......... 46 vii.2 80c188 mod0=1, mod1=1, mod2=0 . . . . ................................. 48 vii.3 80c186 mod0=1, mod1=1, mod2=1 . . . . ................................. 50 vii.4 68000 mod0=0, mod1=0, mod2=1 . . . . . . . . . . . . . . . . . . . . . . . ................ 52 vii.5 token ring timing . ................................................. 54 vii.6 master clock timing . .............................................. 54 contents (continued) page STLC5464 3/83
viii internal registers ................................................ 55 viii.1 identification and dynamic command register . . . . . . . . . . . idcr (00)h 55 viii.2 general configuration . ................................. gcr (02)h 55 viii.3 input multiplex configuration register 0 . . . . . . ......... imcr0 (04)h 57 viii.4 input multiplex configuration register 1 . . . . . . ......... imcr1 (06)h 57 viii.5 output multiplex configuration register 0 . . . . . . . . . . . . omcr0 (08)h 57 viii.6 output multiplex configuration register 1 . . . . . . . . . . . omcr1 (0a)h 58 viii.7 switching matrix configuration register. . . . . . ......... smcr (0c)h 58 viii.8 connection memory data register. . . . . . . . . . . . . . . . . . . . . . cmdr (0e)h 59 viii.9 connection memory address register . . . . . . ............ cmar (10)h 60 viii.10 sequence fault counter register . . . . . . . . . . . . . . . . . . . . . . sfcr (12)h 61 viii.11 time slot assigner address register . . . . . . . . . . . . . . . . . . . taar (14)h 61 viii.12 time slot assigner data register . . . . . . . . . .............. tadr (16)h 62 viii.13 hdlc transmit command register . . . . . . . . . .............. htcr (18)h 62 viii.14 hdlc receive command register . ....................... hrcr (1a)h 64 viii.15 address field recognition address register . . . . . . . . . . afrar (1c)h 65 viii.16 address field recognition data register . . . . . . ........ afrdr (1e)h 66 viii.17 fill character register . . . . ............................. fcr (20)h 66 viii.18 gci channels definition register 0 . . . . . . . . . . . . . . . . . . . . . . gcir0 (22)h 66 viii.19 gci channels definition register 1 . . . . . . . . . . . . . . . . . . . . . . gcir1 (24)h 67 viii.20 gci channels definition register 2 . . . . . . . . . . . . . . . . . . . . . . gcir2 (26)h 67 viii.21 gci channels definition register 3 . . . . . . . . . . . . . . . . . . . . . . gcir3 (28)h 67 viii.22 transmit command / indicate register. . . . . . . . . . . . . . . . . . . . tcir (2a)h 68 viii.23 transmit monitor address register . . . . . . . . . ........... tmar (2c)h 69 viii.24 transmit monitor data register . ....................... tmdr (2e)h 70 viii.25 transmit monitor interrupt register. . . . . . . . . . . . . . . . . . . . tmir (30)h 70 viii.26 memory interface configuration register . . . . . . . . . . . . . . micr (32)h 70 viii.27 initiate block address register. . . . . . . ................... ibar (34)h 72 viii.28 interrupt queue size register . . . . ....................... iqsr (36)h 72 viii.29 interrupt register . . . . . . . . . . . . . . . . . . . . . . . ................. ir (38)h 73 viii.30 interrupt mask register . . . . .............................. imr (3a)h 74 viii.31 time register . . . . . . . . . . . . . . . . . . . . . . . . . . . ................ timr (3c)h 74 viii.32 test register . . . . . . . . . . . . . . . . . . . . . . . . . . . ................... tr (3e)h 74 contents (continued) page STLC5464 4/83
ix external registers ............................................... 75 ix.1 nitialization block in external memory . . . . . . . . . ................... 75 ix.2 receive descriptor . . . . . . . . . . . . . . . . . . . . . . . ......................... 76 ix.2.1 bits written by the microprocessor only . . . . ................................. 76 ix.2.2 bits written by the rx dmac only . ........................................ 76 ix.2.3 receive buffer . ....................................................... 76 ix.3 transmit descriptor . . . . .......................................... 77 ix.3.1 bits written by the microprocessor only . . . . ................................. 77 ix.3.2 bits written by the rx dmac only . ........................................ 78 ix.3.3 transmit buffer . ....................................................... 78 ix.4 receive & transmit hdlc frame interrupt . . . . . . .................... 78 ix.5 receive command / indicate interrupt . . . . . . ....................... 79 ix.5.1 receive command / indicate interrupt when tsv = 0 . . . . . . .................... 79 ix.5.2 receive command / indicate interrupt when tsv = 1 . . . . . . .................... 80 ix.6 receive monitor interrupt . . . . .................................... 80 ix.6.1 receive monitor interrupt when tsv = 0 . . . . . . . ............................. 80 ix.6.2 receive monitor interrupt when tsv = 1 . . . . . . . ............................. 81 x package mechanical data ......................................... 82 contents (continued) page STLC5464 5/83
list of figures page i pin information .................................................... 8 ii block diagram .................................................... 14 figure 1 : general block diagram . . . . . . . . . . . . . . . . . . . . . . . ................ 14 iii functional description ........................................... 15 figure 2 : switching matrix data path . . . . . . . ............................. 16 figure 3 : unidirectional and bidirectional connections . . . . . . . . . ............. 17 figure 4 : loop back . . . . ............................................. 17 figure 5 : variable delay through the matrix with itdm = 1 . . . . . . . . . .......... 18 figure 6 : variable delay through the matrix with itdm = 0 . . . . . . . . . .......... 19 figure 7 : constant delay through the matrix with si = 1 . . . . . . . . . . . . . . . . . . . . . 20 figure 8 : hdlc and dma controller block diagram . . . . . . . . . . . . . . . . . . . . . . . . 22 figure 9 : structure of the receive circular queue . . . . . . . . . ................ 25 figure 10 : structure of the transmit circular queue . . . . . . . . . ................ 25 figure 11 : d, c/i and monitor channel path . . . . . . . . . ...................... 28 figure 12 : multi-hdlc connected to m p with multiplexed buses . . . . . . . . . ....... 29 figure 13 : multi-hdlc connected to m p with non-multiplexed buses . . . . . . . . . . . . 29 figure 14 : microprocessor interface for intel 80c188 . . . . . . ................. 29 figure 15 : microprocessor interface for intel 80c186 . . . . . . ................. 29 figure 16 : microprocessor interface for motorola 68000 . . . . . . . . . .......... 30 figure 17 : microprocessor interface for st9 . . . . . . . . . ...................... 30 figure 18 : 128k x 8 sram circuit memory organization . . . . . . . . . . . . . . . . . . . . . 32 figure 19 : 512k x 8 sram circuit memory organization . . . . . . . . . . . . . . . . . . . . . 32 figure 20 : 256k x 16 dram circuit organization . . . . . . . . . . . . . . . . . . . . . . . .... 32 figure 21 : 1m x 16 dram circuit organization . . . . . . ....................... 33 figure 22 : 4m x 16 dram circuit organization . . . . . . ....................... 33 figure 23 : chain of n multi-hdlc components . . . . . . ....................... 33 figure 24 : mhdlc clock generation . . . . ................................. 34 figure 25 : vcxo frequency synchronization . . . . . . . . . . . . . . . . . . . . . . . ....... 35 figure 26 : the three circular interrupt memories . . . . . . . . . . . . . . . . . . . . . . . .... 36 iv dc specifications .................................................. 37 v clock timing ....................................................... 38 figure 27 : clocks received and delivered by the multi-hdlc .................. 38 figure 28 : synchronization signals received by the multi-hdlc ................ 39 figure 29 : gci synchro signal delivered by the multi-hdlc ................... 40 figure 30 : v* synchronization signal delivered by the multi-hdlc .............. 41 vi memory timing ..................................................... 42 figure 31 : dynamic memory read signals from the multi-hdlc ............... 42 figure 32 : dynamic memory write signals from the multi-hdlc ............... 43 figure 33 : static memory read signals from the multi-hdlc .................. 44 figure 34 : static memory write signals from the multi-hdlc .................. 45 STLC5464 6/83
vii microprocessor timing ............................................ 46 figure 35 : st9 read cycle . ........................................... 46 figure 36 : st9 write cycle . ........................................... 47 figure 37 : 80c188 read cycle . ........................................ 48 figure 38 : 80c188 write cycle . ........................................ 49 figure 39 : 80c186 read cycle . ........................................ 50 figure 40 : 80c186 write cycle . ........................................ 51 figure 41 : 68000 read cycle . . . . . . . . . .................................. 52 figure 42 : 68000 write cycle . . . . ....................................... 53 figure 43 : token ring . . . . . . . . . . . . . . . . . . . . . . . ......................... 54 figure 44 : master clock . .............................................. 54 viii internal registers ................................................ 55 ix external registers ............................................... 75 x package mechanical data ........................................ 82 list of figures (continued) page STLC5464 7/83
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 nce7 nras3/nce6 noe nwe tro tri v ss v dd d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 v ss v dd a23/adm18 a19 a18 a17 a16 nreset xtal1 xtal2 wdo cb ec vcxo in dclk clocka framea v dd v ss fs fscg fscv pss din0 v dd v ss dout0 ndis ntrst tms tdi tdo tck v dd v ss ncs0 int0 nlds nbhe/nuds ndtack nas/ale r/w / nwr nds/nrd mod0 a0/ad0 ntest v ss v dd dm0 adm9 nce5 nras2/nce4 ncas1/nce3 nras1/nce2 ncas0/nce1 nras0/nce0 a22/adm17 a21/adm16 a20/adm15 vcxo out clockb frameb din1 din2 din3 din4 din5 din6 din7 din8 dout1 dout2 dout3 dout4 dout5 dout6 dout7 v dd v ss ncs1 int1 ready mod1 mod2 v dd v ss a1/ad1 a2/ad2 a3/ad3 a4/ad4 a5/ad5 a6/ad6 a7/ad7 a8/ad8 a9/ad9 a10/ad10 a11/ad11 a12/ad12 a13/ad13 a14/ad14 a15/ad15 v ss v dd v ss v dd v ss v dd adm8 adm7 adm6 adm5 adm4 adm3 adm2 adm1 adm0 adm14 adm13 adm12 adm11 adm10 dm1 dm2 dm3 dm4 dm5 dm6 dm8 dm9 dm10 dm7 dm11 dm12 dm13 dm14 dm15 5464-01.eps i - pin information i.1 - pin connections STLC5464 8/83
i.2 - pin description pin n symbol type function power pins (all the power and ground pins must be connected) 14 v dd1 power dc supply 15 v ss1 ground dc ground 29 v dd2 power dc supply 30 v ss2 ground dc ground 45 v dd3 power dc supply 46 v ss3 ground dc ground 61 v dd4 power dc supply 62 v ss4 ground dc ground 73 v dd5 power dc supply 74 v ss5 ground dc ground 89 v dd6 power dc supply 90 v ss6 ground dc ground 107 v dd7 power dc supply 108 v ss7 ground dc ground 121 v dd8 power dc supply 122 v ss8 ground dc ground 133 v dd9 power dc supply 134 v ss9 ground dc ground 145 v dd10 power dc supply 146 v ss10 ground dc ground 158 v dd11 power dc supply 159 v ss11 ground dc ground (total 22) clocks 2 xtal1 i crystal 1. a clock pulse at f min. = 32000khz can be applied to this input (or one pin of two crystal pins) with : -50.10 -6 < d f < +50.10 -6 . 3 xtal2 o crystal 2. if the internal crystal oscillator is used, the second crystal pin is applied to this output. 7 vcxo in o4 vcxo input signal. this signal is compared to clock a(or b) selected inside the multi-hdlc . 8 vcxo out i3 vcxo error signal. this pin delivers the result of the comparison. 10 clocka i3 input clock a (4096khz or 8192khz) 11 clockb i3 input clock b (4096khz or 8192khz) 12 framea i3 clock a at 8khz 13 frameb o8 clock b at 8khz 9 dclk o8 data clock issued from input clock a (or b). this clock is delivered by the circuit at 4096khz (or 2048khz). dout0/7 are transmitted on the rising edge of thissignal. din0/7 are sampled on the falling edge of this signal. 17 fscg o8 frame synchronization for gci at 8khz. this clock is issued from frame a (or b). 18 fscv* i3 frame synchronization for v star at 8khz 16 fs o8 frame synchronization.this signal synchronizes din0/7 and dout0/7. 19 pss i3 programmable synchronization signal. the ps bit of connection memory is read in real time. type : i1 = input ttl ; i2 = i1 + pull-up ; i3 = i1 + hysteresis ; i4 = i3 + pull-up ; o4 = output cmos 4ma ; o4t = o4 + tristate ; o8 = output cmos 8ma, o1o and o0o at low impedance ; o8d = output cmos 8ma, open drain ; o8dt = output cmos 8ma, open drain or tristate ; o8t = output cmos 8ma, tristate i - pin information (continued) STLC5464 9/83
i.2 - pin description (continued) pin n symbol type function time division multiplexes (tdm) 20 din0 i1 tdm0 data input 0 21 din1 i1 tdm1 data input 1 22 din2 i1 tdm2 data input 2 23 din3 i1 tdm3 data input 3 24 din4 i1 tdm4 data input 4 25 din5 i1 tdm5 data input 5 26 din6 i1 tdm6 data input 6 27 din7 i1 tdm7 data input 7 28 din8 i1 tdm8 data input 8 31 dout0 o8dt tdm0 data output 0 32 dout1 o8dt tdm1 data output 1 33 dout2 o8dt tdm2 data output 2 34 dout3 o8dt tdm3 data output 3 35 dout4 o8dt tdm4 data output 4 36 dout5 o8dt tdm5 data output 5 37 dout6 o8dt tdm6 data output 6 38 dout7 o8dt tdm7 data output 7 39 ndis i1 dout 0/7 not disable. when this pin is at 0v, the data output 0/7 are at high impedance. wired at vdd if not used. 5 cb o8d contention bus for csma/cr 6 ec i1 echo. wired at vss if not used. boudary scan 40 ntrst i4 reset for boundary scan 41 tms i2 mode selection for boundary scan 42 tdi i2 input data for boundary scan 43 tdo o4 output data for boundary scan 44 tck i4 clock for boundary scan microprocessor interface 58 mod0 i1 1 1 0 1 59 mod1 i1 1 1 0 0 60 mod2 i1 0 1 1 0 80c188 80c186 68000 st9 1 nreset i3 circuit reset 47 ncs0 i3 chip select 0 : internal registers are selected 48 ncs1 i3 chip select 1 : external memory is selected 49 int0 o4 interrupt generated by hdlc, rxc/i or rxmon. active high. 50 int1 o4 interrupt1.this pin goes to 5v when the selected clock a (or b) has disappeared ; 250 m s after reset this pin goes to 5v also if clock a is not present. 4 wdo o4 watch dog output.this pin goes to 5v during 1ms when the microprocessor has not reset the watch dog during the programmable time. type : i1 = input ttl ; i2 = i1 + pull-up ; i3 = i1 + hysteresis ; i4 = i3 + pull-up ; o4 = output cmos 4ma ; o4t = o4 + tristate ; o8 = output cmos 8ma, o1o and o0o at low impedance ; o8d = output cmos 8ma, open drain ; o8dt = output cmos 8ma, open drain or tristate ; o8t = output cmos 8ma, tristate i - pin information (continued) STLC5464 10/83
i.2 - pin description (continued) pin n symbol type function microprocessor interface (continued) 51 nlds i3 lower data strobe (68000) 52 nuds i3 bus high enable (intel) / upper data strobe (68000) 53 ndtack o8d data transfer acknowledge (68000) 54 ready o8t data transfer acknowledge (intel) 55 nas/ale i3 address strobe(motorola) / addresss latch enable(intel) 56 r/w / nwr i3 read/write (motorola) / write(intel) 57 nds/nrd i3 data strobe (motorola) /read data (intel) 63 a0/ad0 i/o address bit 0 (motorola) / address/data bit 0 (intel) 64 a1/ad1 i/o address bit 1 (motorola) / address/data bit 1 (intel) 65 a2/ad2 i/o address bit 2 (motorola) / address/data bit 2 (intel) 66 a3/ad3 i/o address bit 3 (motorola) / address/data bit 3 (intel) 67 a4/ad4 i/o address bit 4 (motorola) / address/data bit 4 (intel) 68 a5/ad5 i/o address bit 5 (motorola) / address/data bit 5 (intel) 69 a6/ad6 i/o address bit 6 (motorola) / address/data bit 6 (intel) 70 a7/ad7 i/o address bit 7 (motorola) / address/data bit 7 (intel) 71 a8/ad8 i/o address bit 8 (motorola) / address/data bit 8 (intel) 72 a9/ad9 i/o address bit 9 (motorola) / address/data bit 9 (intel) 75 a10/ad10 i/o address bit 10 (motorola) / address/data bit 10 (intel) 76 a11/ad11 i/o address bit 11 (motorola) / address/data bit 11 (intel) 77 a12/ad12 i/o address bit 12 (motorola) / address/data bit 12 (intel) 78 a13/ad13 i/o address bit 13 (motorola) / address/data bit 13 (intel) 79 a14/ad14 i/o address bit14 (motorola) / address/data bit 14 (intel) 80 a15/ad15 i/o address bit15 (motorola) / address/data bit 15 (intel) 81 a16 i1 address bit16 (motorola) / address bit 16 (intel) 82 a17 i1 address bit17 (motorola) / address bit 17 (intel) 83 a18 i1 address bit18 (motorola) / address bit 18 (intel) 84 a19 i1 address bit19 (motorola) / address bit 19 (intel) 85 a20/adm15 i/o address bit 20 from m p (input) / address bit 15 for sram (output) 86 a21/adm16 i/o address bit 21 from m p (input) / address bit 16 for sram (output) 87 a22/adm17 i/o address bit 22 from m p (input) / address bit 17 for sram (output) 88 a23/adm18 i/o address bit 23 from m p (input) / address bit 18 for sram (output) 91 do i/o data bit 0 for m p if not multiplexed (see note 1). 92 d1 i/o data bit 1 for m p if not multiplexed 93 d2 i/o data bit 2 for m p if not multiplexed 94 d3 i/o data bit 3 for m p if not multiplexed 95 d4 i/o data bit 4 for m p if not multiplexed 96 d5 i/o data bit 5 for m p if not multiplexed 97 d6 i/o data bit 6 for m p if not multiplexed 98 d7 i/o data bit 7 for m p if not multiplexed 99 d8 i/o data bit 8 for m p if not multiplexed type : i1 = input ttl ; i2 = i1 + pull-up ; i3 = i1 + hysteresis ; i4 = i3 + pull-up ; o4 = output cmos 4ma ; o4t = o4 + tristate ; o8 = output cmos 8ma, o1o and o0o at low impedance ; o8d = output cmos 8ma, open drain ; o8dt = output cmos 8ma, open drain or tristate ; o8t = output cmos 8ma, tristate i - pin information (continued) STLC5464 11/83
i.2 - pin description (continued) pin n symbol type function microprocessor interface (continued) 100 d9 i/o data bit 9 for m p if not multiplexed 101 d10 i/o data bit 10 for m p if not multiplexed 102 d11 i/o data bit 11 for m p if not multiplexed 103 d12 i/o data bit 12 for m p if not multiplexed 104 d13 i/o data bit 13 for m p if not multiplexed 105 d14 i/o data bit 14 for m p if not multiplexed 106 d15 i/o data bit 15 for m p if not multiplexed memory interface 109 tri i3 token ring input (for use multi-hdlc s in cascade) 110 tro o4 token ring output (for use multi-hdlc s in cascade) 111 nwe o4t write enable for memory circuits 112 noe o4t control output enable for memory circuits 113 nras0/nce0 o4t row address strobe bank 0 / chip enable 0 for sram 114 ncas0/nce1 o4t column address strobe bank 0 / chip enable1 for sram 115 nras1/nce2 o4t row address strobe bank 1 / chip enable 2 for sram 116 ncas1/nce3 o4t column address strobe bank 1 / chip enable 3 for sram 117 nras2/nce4 o4t row address strobe bank 2 / chip enable 4 for sram 118 nce5 o4t chip enable 5 for sram 119 nras3/nce6 o4t row address strobe bank 3 / chip enable 6 for sram 120 nce7 o4t chip enable 7 for sram 123 adm0 o8t address bit 0 for sram and dram 124 adm1 o8t address bit 1 for sram and dram 125 adm2 o8t address bit 2 for sram and dram 126 adm3 o8t address bit 3 for sram and dram 127 adm4 o8t address bit 4 for sram and dram 128 adm5 o8t address bit 5 for sram and dram 129 adm6 o8t address bit 6 for sram and dram 130 adm7 o8t address bit 7 for sram and dram 131 adm8 o8t address bit 8 for sram and dram 132 adm9 o8t address bit 9 for sram and dram 135 adm10 o8t address bit 10 for sram and dram 136 adm11 o8t address bit 11 for sram only 137 adm12 o8t address bit 12 for sram only 138 adm13 o8t address bit 13 for sram only 139 adm14 o8t address bit 14 for sram only type : i1 = input ttl ; i2 = i1 + pull-up ; i3 = i1 + hysteresis ; i4 = i3 + pull-up ; o4 = output cmos 4ma ; o4t = o4 + tristate ; o8 = output cmos 8ma, o1o and o0o at low impedance ; o8d = output cmos 8ma, open drain ; o8dt = output cmos 8ma, open drain or tristate ; o8t = output cmos 8ma, tristate i - pin information (continued) STLC5464 12/83
i.2 - pin description (continued) pin n symbol type function memory interface (continued) 140 dm0 i/o memory data bit 0 141 dm1 i/o memory data bit 1 142 dm2 i/o memory data bit 2 143 dm3 i/o memory data bit 3 144 dm4 i/o memory data bit 4 147 dm5 i/o memory data bit 5 148 dm6 i/o memory data bit 6 149 dm7 i/o memory data bit 7 150 dm8 i/o memory data bit 8 151 dm9 i/o memory data bit 9 152 dm10 i/o memory data bit 10 153 dm11 i/o memory data bit 11 154 dm12 i/o memory data bit 12 155 dm13 i/o memory data bit 13 156 dm14 i/o memory data bit 14 157 dm15 i/o memory data bit 15 160 ntest i2 test control. when this pin is at 0v each output is high impedance except xtal2 pin. type : i1 = input ttl ; i2 = i1 + pull-up ; i3 = i1 + hysteresis ; i4 = i3 + pull-up ; o4 = output cmos 4ma ; o4t = o4 + tristate ; o8 = output cmos 8ma, o1o and o0o at low impedance ; o8d = output cmos 8ma, open drain ; o8dt = output cmos 8ma, open drain or tristate ; o8t = output cmos 8ma, tristate note : d0/15 input/output pins must be connected to one single external pull up resistor if not used. i.3 - pin definition i.3.1 - input pin definition i1 : input 1 ttl i2 : input 2 ttl + pull-up i3 : input 3 ttl + hysteresis i4 : input 4 ttl + hysteresis +pull-up i.3.2 - output pin definition o4 : output cmos 4ma o4t : output cmos 4ma, tristate o8 : output cmos 8ma o8t : output cmos 8ma,tristate o8d : output cmos 8ma,open drain o8dt : output cmos 8ma,open drain or tristate (programmable pin) moreover, each output is high impedance when the ntest pin is at 0 volt except xtal2 pin. i.3.3 - input/output pin definition i/o : input ttl/ output cmos 8ma. n.b. xtal1 : this input is cmos. xtal2 : ntest pin at 0 has no effect on this pin. i - pin information (continued) STLC5464 13/83
pseudo random sequence generator 7 counter xtal watchdog m p interface clock selection ram interface 8 2 3 28 4 27 26 vcx out xtal1 xtal2 din8 wdo gci1 gci0 25 24 23 22 21 20 din5 din4 din3 din2 din1 din0 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 d7 pseudo random sequence analyser 39 31 32 33 34 ndis dout0 dout1 dout2 dout3 switching matrix n x 64 kb/s 35 gci0 36 dout4 dout5 37 dout6 gci1 38 dout7 12 frame a 10 clock a 13 frame b 11 clock b 18 17 9 fscv* fscg dclk to internal circuit 16 fs 5cb time slot assigner for multihdlc gci channel definition v10 32 rx hdlc with adress recognition 32 rx dmac 16 rx c/i 16 rx mon 16 tx c/i 16 tx mon 6ec 32 tx hdlc with csma cr for content. bus 32 tx dmac m p bus interrupt controller rx c/i rx mon tx c/i tx mon ram bus 49 int0 50 int1 internal bus bus arbitration STLC5464 v10 vcx in din7 din6 5464-02.eps figure 1 : general block diagram ii - block diagram the top level functionalities of multi-hdlc appear on the general block diagram. there are : - the switching matrix, - the time slot assigner, - the 32 hdlc transmitters with associated dma controllers, - the 32 hdlc receivers with associated dma controllers, - the 16 command/indicate and monitor channel transmitters belonging to two general compo- nent interfaces(gci), - the 16 command/indicate and monitor channel receivers belonging to two general component interfaces (gci), - the memory interface, - the microprocessor interface, - the bus arbitration, - the clock selection and time synchronization function, - the interrupt controller, - the watchdog, STLC5464 14/83
iii - functional description iii.1 - the switching matrix n x 64 kbits/s iii.1.1 - function description the matrix performs a non-blocking switch of 256 time slots from 8 input time division multiplex (tdm) at 2 mbit/s to 8 output time division multi- plex. a tdm is composed of 32 time slots (ts) at 64 kbit/s. the matrix is designed to switch a 64 kbit/s channel (variable delay mode) or an hyper- channel of data (sequence integrity mode). so, it will both provide minimum throughput switching delay for voice applications and time slot sequence integrity for data applications on a per channel basis. the requirements of the sequence integrity (n*64 kbit/s) mode are the following: all the time slots of a given input frame must be put out during a same output frame. the time slots of an hyperchannel (concatenation of ts in the same tdm) are not crossed together at output in different frames. in variable delay mode, the time slot is put out as soon as possible. (the delay is two or three time slots minimum between input and output). for test facilities, any time slot of an output tdm (otdm) can be internally looped back into the same input tdm number (itdm) at the same time slot number. a pseudo random sequence generator and a pseudo random sequence analyzer are imple- mented in the matrix. they allow the generation a sequence on a channel or on a hyperchannel, to analyse it and verify its integrity after several switching in the matrix or some passing of the sequence across different boards. the frame signal (fs) synchronises itdm and otdm but a programmable delay or advance can be introduced separatelyon each itdm and otdm (a half bit time, a bit time or two bit times). an additional pin (pss) permits the generation of a programmable signal composed of 256 bits per frame at a bit rate of 2048 kbit/s. an external pin (ndis) asserts a high impedance on all the tdm outputs of the matrix when active (during the initialization of the board for example). iii.1.2 - architecture of the matrix the matrix is essentially composed of buffer data memories and a connection memory. the received serial data is first converted to parallel by a serial to parallelconverterand stored consecu- tively in a 256 position buffer data memory (see figure 2 on page 16). to satisfy the sequence integrity (n*64 kbit/s) re- quirements, the data memory is built with an even memory, an odd memory and an output memory. two consecutive frames are stored alternatively in the odd and even memory. during the time an input frame is stored, the one previously stored is trans- ferred into the output memory according to the connectionmemoryswitching orders. aframe later, the output memory is read and data is converted to serial and transferred to the output tdm. iii.1.3 - connection function two types of connections are offered : - unidirectional connection and - bidirectional connection. an unidirectionalconnection makes only the switch of an input time slot through an output one whereas a bidirectionalconnectionestablishesthe link in the other direction too. so a double connection can be achieved by a single command (see figure 3 on page 17). iii.1.4 - loop back function any time slot of an output tdm can be internally looped back on the time slot which has the same tdm number and the same ts number (otdmi, tsj) ----> (itdmi, tsj). in the case of a bidirectional connection, only the one specified by the microprocessor is concerned by the loop back (see figure 4 on page 17). STLC5464 15/83
from smcr register cm (when read) loop data memories 64kb/s and n x 64kb/s connection memory sequence integrity, loop, prsa, prsg, ins, otsv tx hdlc rx gci s/p imtd sequence integrity ins 1 1 a 1 cm 1 prsg pseudo random sequence generator 2 11 -1 rec. o.152 prsg sgv pseudo random sequence analyzer 2 11 -1 rec. o.152 prsa sav gcir bit synchro tx gci me p/s rx hdlc d4/5 d7 d0/7 1 1 dd 1 cmdr data register cmar address register sfdr sequence fault counter register hdlcm 1 d7 din' 0/7 d4/5 bit synchro din 0/7 dout 0/7 internal bus from omcr register omv (per multiplex) from connection memory otsv (per channel) from disable pin (for all multiplexes) prsg : pseudo random sequence generator prsa : pseudo random sequence analyzer otsv : output time slot validated ins : insert me : message enable imtd : increased min throughtput delay sgv : sequence generator validated sav : sequence analyzer validated cm : connection memory (from cmar register) from connection memory 5464-03.eps figure 2 : switching matrix data path iii - functional description (continued) STLC5464 16/83
otsy, otdmq data memory n x 64kb/s data memory n x 64kb/s down stream itsy, itdmq up stream itsx,itdmp down stream otsx, otdmp up stream bidirectional connection otsy, otdmq data memory n x 64kb/s down stream itsx,itdmp down stream unidirectional connection p, q = 0 to 7 x, y = 0 to 31 5464-04.eps figure 3 : unidirectional and bidirectional connections otsy, otdmq data memory n x 64kb/s data memory n x 64kb/s down stream itsy, itdmq up stream itsx,itdmp down stream otsx, otdmp up stream otsv loop loopback per channel relevant if bidirectional connection has been done. p, q = 0 to 7 x, y = 0 to 31 5464-05.eps figure 4 : loop back iii - functional description (continued) iii.1.5 - delay through the matrix iii.1.5.1 - variable delay mode in the variable delay mode, the delay through the matrix dependson the relative positionsof the input and output time slots in the frame. so, some limits are fixed : - the maximum delay is a frame + 2 time slots, - the minimum delay is programmable. three time slots if imtd = 1, in this case n = 2 in the formula hereafter or two time slots if imtd = 0, in this case n = 1 in the same formula (see paragraph oswitching matrix configuration reg smcr (0c)ho on page 60). all the possibilities can be ranked in three cases : a) if otsy > itsx + n then the variable delay is : otsy - itsx time slots b) if itsx < otsy < itsx + n then the variable delay is : otsy - itsx + 32 time slots c) otsy < itsx then the variable delay is : 32 - (itsx - otsy) time slots. n.b. rule b) and rule c) are identical. for n = 1 and n = 2, see figure 5 on page 18. iii.1.5.2 - sequence integrity mode in the sequence integrity mode (si = 1, bit located in the connection memory), the input time slots are put out 2 frames later (see figure 6 on page 19). in this case, the delay is definedby a singleexpres- sion : constant delay = (32 - itsx) + 32 + otsy so, the delay in sequence integrity mode varies from 33 to 95 time slots. STLC5464 17/83
frame n frame n + 1 its0 its31 its0 its 31 ots0 ots31 its x its x+1 itsx+2 otsy y>x+2 variable de lay (ots y - itsx) input frame output frame 1) ca s e : if ots y > its x + 2, the n va ria ble de la y is : ots y - itsx time s lo ts frame n frame n + 1 its0 its31 its0 its 31 ots0 ots31 its x its x+1 itsx+2 otsy x y x+2 32 time s lots va riable de lay : ots y - itsx + 32 time s lots input frame output frame 2) ca s e : if its x otsy its x + 2, the n variab le de la y is : o ts y - its x + 32 tim es lots itsx otsy frame n frame n + 1 its0 its31 its0 its 31 ots0 ots31 its x otsy ySTLC5464 18/83
frame n frame n + 1 its0 its31 its0 its31 ots0 ots31 itsx itsx+1 itsx+2 otsy y>x+1 variable delay (otsy - itsx) input frame output frame 1) case : if otsy > itsx + 1, then variable delay is : otsy - itsx timeslots frame n frame n + 1 its0 its31 its0 its31 ots0 ots31 itsx itsx+1 itsx+2 otsy x y x+1 32 timeslots variable delay : otsy - itsx + 32 timeslots input frame output frame 2) case : if itsx otsy itsx + 1, then variable delay is : otsy - itsx + 32 timeslots itsx otsy frame n frame n + 1 its0 its31 its0 its31 ots0 ots31 itsx otsy ySTLC5464 19/83
co ns ta nt delay = (32 -itsx) + 32 + ots y framen framen+1 framen+2 its0 min. consta nt delay = 33ts 32 time s lots + 0 = 33 time s lots max. consta nt delay = 95 time slots 32 - 0 + 32 + 31 = 95 time s lots (32 - itsx) +32 +otsy =constant delay its31 its0 its31 its0 its31 ots0 ots31 1+ ots 31 its : ots : input time s lot output times lot 0 x 31 0 y 31 5464-08.eps figure 7 : constant delay through the matrix with si = 1 iii - functional description (continued) STLC5464 20/83
iii.1.6 - connection memory iii.1.6.1 - description the connection memory is composed of 256 loca- tions addressed by the number of otdm and ts (8x32). each location permits : - to connect each input time slot to one output time slot (if two or more output time slots are con- nected to the same input time slot number, there is broadcasting). - to selectthe variable delay mode or the sequence integrity mode for any time slot. - to loop back an output time slot. in this case the contents of an input time slot (itsx, itdmp) is the same as the output time slot (otsx,otdmp). - to output the contents of the corresponding con- nection memory instead of the data which has been stored in data memory. - to output the sequence of the pseudo random sequence generator on an output time slot: a pseudo random sequence can be inserted in one or several time slots (hyperchannel) of the same output tdm ; this insertion must be enabled by the microprocessor in the configuration register of the matrix. - to define the source of a sequenceby the pseudo random sequence analyzer: a pseudo random sequence can be extracted from one or several time slots (hyperchannel)of the same input tdm and routed to the analyzer; this extraction can be enabled by the microprocessor in the configura- tion register of the matrix (smcr). - to assert a high impedance level on an output time slot (disconnection). - to deliver a programmable 256-bit sequence dur- ing 125 microsecondson the programmable syn- chronization signal pin (pss). iii.1.6.2 - access to connection memory supposing that the switching matrix configuration register (smcr) has been already written by the microprocessor, it is possible to access to the con- nection memory from microprocessor with the help of two registers : - connection memory data register (cmdr) and - connection memory address register (cmar). iii.1.6.3 - access to data memory to extract the contents of the data memory it is possible to read the data memory from microproc- essor with the help of the two registers : - connection memory data register (cmdr) and - connection memory address register (cmar). iii.2 - hdlc controller iii.2.1 - function description the internal hdlc controller can run up to 32 channels in a conventional hdlc mode or in a transparent (non-hdlc) mode (configurable per channel). each channel bit rate is programmable from 4kbit/s to 64kbit/s. all the configurations are also possible from 32 channels (from 4 to 64 kbit/s) to one channel at 2 mbit/s. in reception,the hdlc time slots can directly come from the input tdm din8 (direct hdlc input) or from any other tdm input after switching towards the output 7 of the matrix (configurable per time slot). in transmission, the hdlc frames are sent on the output dout6 and on the output cb (with or with- out contention mechanism), or are switched to- wards the other tdm output via the input 7 of the matrix (see figure 8 on page 22 and paragraph iii.2.2 on page 23). iii.2.1.1 - format of the hdlc frame the format of an hdlc frame isthe same in receive and transmit direction and shown here after. iii.2.1.2 - composition of an hdlc frame opening flag address field (first byte) address field (second byte) command field (first byte) command field (second byte) data (first byte) data (optional) data (last byte) fcs (first byte) fcs (second byte) closing flag - opening flag - one or two bytes for address recognition (recep- tion) and insertion (transmission) - data bytes with bit stuffing - frame check sequence: crc with polynomial g(x) = x16 +x12+x5+1 - closing flag. iii - functional description (continued) STLC5464 21/83
time s lot as s igne r 32 rx hdlc 32 addre s s recognition 32 rx fifo 's 32 rx dmac 32 rx dmac 32 tx fifo 's 32 tx hdlc 32 cs ma-cr din 8 dire ct hdlc i nput f rom output 7 of the matrix to input 7 of the matrix from output 6 of the matrix dout 6 direct hdlc o utput conte ntion bus echo m p interface ram interface 5464-09.eps figure 8 : hdlc and dma controller block diagram iii - functional description (continued) STLC5464 22/83
iii.2.1.3 - description and functions of the hdlc bytes - flag the binary sequence 01111110 marks the begin- ning and the end of the hdlc frame. note : in reception, three possible flag configura- tions are allowed and correctly detected : - two normal consecutive flags : ...01 111110 011111 10... - two consecutive flags with a o0o common : ...01 1111101111110... - a global common flag : ...01 111110... this flag is the closing flag for the current frame and the opening flag for the next frame - abort the binary sequence 1 111111 marks an abort command. in reception, seven consecutive1's, inside a mes- sage, are detected as an abort command and generates an interrupt to the host. in transmit direction, an abort is sent upon com- mand of the micro-processor. no ending flag is expected after the abort command. - bit stuffing and unstuffing this operation is done to avoid the confusion of a data byte with a flag. in transmission, if five consecutive 1's appear in the serial stream being transmitted,a zero isauto- matically inserted (bit stuffing) after he fifth o1o. in reception, if five consecutive o1o followed by a zero are received, the o0o is assumed to have been inserted and is automatically deleted (bit unstuffing). - frame check sequence the frame check sequenceis calculatedaccording to the recommendationq921 of the ccitt. - address recognition in the frame, one or two bytes are transmitted to indicate the destination of the message. two types of addresses are possible : - a specific destination address - a broadcast address. in reception, the controller compares the receive addresses to internal registers, which contain the address message. 4 bits in the receive command register (hrcr) inform the receiver of which registers, it has to take into account for the com- parison. the receiver compares the two address bytes of the message to the specific board ad- dress and the broadcast address. upon an ad- dress match, the address and the data following are written to the data buffers; upon an address mismatch, the frame is ignored. so, it authorizes the filtering of the messages. if no comparison is specified, each frame is received whatever its address field. in transmission, the controller sends the frame in- cluding the destination or broadcastaddresses. iii.2.2 - csma/cr capability an hdlc channel can come in and go out by any tdm input on the matrix. for time constraints, direct hdlc access is achieved by the input tdm (din 8) and the output tdm (dout6). in transmission, a time slot of a tdm can be shared between different sources in multi-point to point configuration (different subscriber's boards for ex- ample). the arbitration system is the csma/cr (carrier sense multiple access with contention resolution). the contention is resolved by a bus connected to the cb pin (contention bus). this bus is a 2mbit/s wire line common to all the potential sources. if a multi-hdlc has obtained the access to the bus, the data to transmit is sent simultaneouslyon the cb line and the outputtdm. theresult of the contention is read backon the echoline.if a collisionisdetected, the transmission is stopped immediately. a conten- tionon a bit basisis so achieved. each message to be sent with csma/cr has a priority class (pri = 8, 10) indicated by the transmit descriptor and some rules are implemented to arbitrate the access to the line. the csma/cr algorithm is given. when a request to send a message occurs, the trans- mitter determines if the shared channel is free. the multi-hdlc listens to the echo line. if c or more consecutive o1o are detected (c depending on the message's priority), the multi-hdlc begins to send its message. each bit sent is sampled back and compared with the original value to send. if a bit is different, the transmission is instantaneously stopped (before the end of this bit time) and will restart as soon as the multi-hdlc will detect thatthe channel is free without interrupting the microproc- essor. after a successful transmission of a message, a programmablepenalty pen(1 or 2) isapplied to the transmitter (see paragraph hdlc transmit com- mand register on page 65). it guaranteesthat the same transmitterwill not take the bus another time before a transmitter which has to send a message of same priority. in case of a collision, the frame which has been aborted is automatically retransmitted by the dma controller without warning the microprocessor of this collision. the frame can be located in several buffers in external memory. the collision can be detected from the second bit of the opening frame to the last but one bit of the closing frame. iii - functional description (continued) STLC5464 23/83
iii.2.3 - time slot assigner memory each hdlc channel is bidirectional and configu- rate by the time slot assigner (tsa). the tsais a memoryof 32 words (one per physical time slot) where all of the 32 input and output time slots of the hdlc controllers can be associated to logical hdlc channels. super channels are created by assigning the same logical channel number to several physical time slots. the following features are configurate for each hdlc time slot : - time slot used or not - one logical channel number - its source : (din 8 or the output 7 of the matrix) - its bit rate and concerned bits (4kbit/s to 64kbit/s). 4kbit/s correspond to one bit transmit- ted each two frames. this bit must be present in two consecutive frames in reception, and re- peated twice in transmission. - its destination : - direct output on dout6 - direct output on dout6 and on the contention bus (cb) - on another otdm via input 7 of the matrix and on the contention bus (cb) iii.2.4 - data storage structure data associated with each rx and tx hdlc chan- nel is stored in externalmemory; the data transfers between the hdlc controllers and memory are ensuredby 32 dmac(direct memory accesscon- troller) in reception and 32 dmac in transmission. the storage structure chosen in both directions is composed of one circular queue of buffers per channel. in such a queue, each data buffer is pointed to by a descriptor located in external mem- ory too. the main information contained in the descriptor is the address of the data buffer, its length and the address of the next descriptor; so the descriptors can be linked together. this structure allows to : - store receive frames of variable and unknown length - read transmit frames stored in external memory by the host - easily perform the frame relay function. iii.2.4.1 - reception at the initialization of the application, the host has to prepare an initialization block memory, which contains the first receive buffer descriptor address for each channel, and the receive circular queues. at the opening of a receive channel, the dma controller reads the address of the first buffer de- scriptor corresponding to this channel in the initiali- zation block. then, the data transfer can occur without intervention of the processor (see figure 9 on page 25). a new hdlc frame always begins in a new buffer. a long frame can be split between several buffers if the buffer size is not sufficient. all the information concerning the frame and its location in the circular queue is included in the receive buffer descriptor : - the receive buffer address (rba), - the size of the receive buffer (sob), - the number of byteswritten into the buffer (nbr), - the next receive descriptor address (nrda), - the status concerning the receive frame, - the control of the queue. iii.2.4.2 - transmission in transmission, the data is managed by a similar structure as in reception (see figure 10 on page 25). by the same way, a frame can be split up between consecutive transmit buffers. the main information contained in the transmit descriptor are : - transmit buffer address (tba), - numberof bytes to transmit(nbt) concerningthe buffer, - next transmit descriptor address (ntda), - status of the frame after transmission, - control bit of the queue, - csma/cr priority (8 or 10). iii.2.4.3 - frame relay the principle of the frame relay is to transmit a frame which has been received without treatment. a new heading is just added. this will be easily achieved, taking into account that the queue struc- ture allows the transmission of a frame split be- tween several buffers. iii - functional description (continued) STLC5464 24/83
receive dma controller rda 0 rda 1 initialization block up to 32 channels rda 31 receive buffer n receive descriptor n nrda rba receive buffer 2 nrda rba receive descriptor 2 receive buffer 1 nrda rba initial receive descriptor receive buffer 3 receive descriptor 3 nrda rba one receive circular queue by channel 5464-10.eps figure 9 : structure of the receive circular queue iii - functional description (continued) transmit dma controller tda 0 tda 1 initialization block up to 32 channels tda 31 transmit buffer n transmit descriptor n ntda tba transmit buffer 2 ntda tba transmit descriptor 2 transmit buffer 1 ntda tba initial transmit descriptor transmit buffer 3 transmit descriptor 3 ntda tba one transmit circular queue by channel 5464-11.eps figure 10 : structure of the transmit circular queue STLC5464 25/83
iii.2.5 - transparent modes in the transparentmode, the multi-hdlc transmits data in a completely transparent manner without performing any bit manipulation or flag insertion. the transparent mode is per byte function. two transparent modes are offered : - first mode : for the receive channels, the multi-hdlc continuously writes received bytes into the external memory as specified in the cur- rent receive descriptor without taking intoaccount the fill character register. - second mode : the fill character register specifies the ofill charactero which must be taken into account. in reception,the ofill characterowill not be transferred to theexternalmemory. the detectionof ofill charac- tero marks the end of a message and generates an interruptifbint=1 (see transmitdescriptoronpage 78). when the ofill characterois not detected a new message is receiving. as for the hdlc mode the correspondence between the physical time slot and the logical channel is fully defined in the time slot assigner memory (time slot used or not used, logical chan- nel number, source, destination). iii.2.6 - command of the hdlc channels the microprocessor is able to control each hdlc receive and transmit channel. some of the com- mands are specific to the transmission or the re- ception but others are identical. iii.2.6.1 - reception control the configuration of the controller operating mode is: hdlc mode or transparent mode. the control of the controller: start, halt, con- tinue, abort. - start : on a start command, the rxdma con- troller reads the address of the first descriptor in the initialization block memory and is ready to receive a frame. - halt : for overloading reasons, the microproc- essor can decide to halt the reception. the dma controller finishes transfer of the current frame to external memory and stops. the channel can be restarted on continue command. - continue : the reception restarts in the next descriptor. - abort: on an abort command, the reception is instantaneously stopped. the channel can be restarted on a start or continue command. reception of flag (01 111110) or idle (1 1111111) between frames. address recognition. the microprocessor defines the addressesthat the rx controller has to take into account. in transparent mode: ofill charactero register se- lected or not. iii.2.6.2 - transmission control the configuration of the controller operating mode is : hdlc mode or transparent mode. the control of the controller : start, halt, con- tinue, abort. - start : on a start command, the tx dmacontrol- ler reads the address of the first descriptor in the initialization block memory and tries to transmit the first frame if end of queue is not at o1o. - halt : the transmitter finishes to send the cur- rent frame and stops.the channel can be restart- ed on a continue command. - continue : if the continue command occurs after halt command, the hdlc transmitter re- starts by transmitting the next buffer associated to the next descriptor. if the continue command occurs after an abort command which has occurred during a frame, the hdlc transmitter restarts by transmit- ting the frame which has been effectively aborted by the microprocessor. - abort: on an abort command, the transmission of the current frame is instantaneously stopped, an abort sequence o1 111111o is sent, followed by idle or flag bytes. the channel can be restarted on a start or continue command. transmission of flag (01111110 ) or idle (111111111) between frames can be selected. crc can be generated or not. if the crc is not generated by the hdlc controller, it must be lo- cated in the shared memory. in transparentmode: ofill charactero register can be selected or not. iii.3 - c/i and monitor iii.3.1 - function description the multi-hdlc is able to operate both gci and v* links. the tdm din/dout 4 and 5 are internally connected to the ci and monitor receivers/trans- mitters. since the controllers handle up to 16 ci and 16 monitor channels simultaneously, the multi- hdlc can manage up to 16 level 1 circuits. the multi-hdlc can be used to support the ci and monitor channels based on the following proto- cols : - isdn v* protocol - isdn gci protocol - analog gci protocol. iii - functional description (continued) STLC5464 26/83
iii.3.2 - gci and v* protocol a tdm can carry 8 gci channels or v* channels. the monitor and s/c bytes always stand at the same position in the tdm in both cases. cgi channel 0 cgi channel 1 to channel 6 cgi channel 7 ts0 ts1 ts2 ts3 ts28 ts29 ts30 ts31 b1 b2 mon s/c b1 b2 mon s/c iii - functional description (continued) the gci or v* channels are composed of 4 bytes and have both the same general structure. b1 b2 mon s/c b1, b2 : bytes of data. those bytes are not affected by the monitor and ci protocols. mon : monitor channel for operation and maintenance information. s/c : signalling and control information. only monitor handshakes and s/c bytes are dif- ferent in the three protocols : isdn v* s/c byte d c/i 4 bits t e isdn gci s/c byte d c/i 4 bits a e analog gci s/c byte c/i 6 bits a e ci : the command/indicate channel is used for activation/deactivation of lines and control functions. d : these 2 bits carry the 16 kbit/s isdn basic access d channel. in gci protocol, a and e are the handshake bits and are used to control the transfer of information on monitor channels.the e bit indicates the trans- fer of each new byte in one direction and the a bit acknowledges this byte transfer in the reverse di- rection. in v* protocol, there isn't any handshakemode.the transmitter has only to mark the validity of the monitor byte by positioning the e bit (t is not used and is forced to o1o). for more information about the gci and v*, refer to the general interface circuit specification (is- sue1.0, march 1989) and the france telecom specification about isdn basic access second generation (november 1990). iii.3.3 - structure of the treatment gci/v* tdm's are connected to din 4 and din 5. the d channels are switched through the matrix towards the output 7 and the hdlc receiver. the monitor and s/c bytes are multiplexed and sent to the ci and monitor receivers (see figure 11 on page 28). in transmission, the s/c and monitor bytes are recombined by multiplexing the information pro- vided by the monitor,c/i and the hdlctransmitter. like in reception,the d channelis switched through the matrix. iii.3.4 - ci and monitor channel configuration monitor channel data is located in a time slot ; the ci and monitor handshakebits are in the next time slot. each channel can be defined independently. a table with all the possible configurations is pre- sented hereafter (table 13). table 13 : c/i and mon channel configuration c/i validated or not ci for analog subscriber (6 bits) ci for isdn subscriber (4 bits) monitor validated or not monitor v* monitor gci note : a mix of v* and gci monitoring can be performed for two distinct channels in the same application. iii.3.5 - ci and monitor transmission/reception command the reception of c/i and monitor messages are managed by two interrupt queues. in transmission, a transmit command register is implemented for each c/i and monitor channel (16 c/i transmit command registers and 16 monitor transmit command registers). those registers are accessible in read and write modes by the micro- processor. STLC5464 27/83
iii - functional description (continued) 16 rx c/i 16 rx mon 16 tx c/i 16 tx mon interrupt contr oller gci channel definition din 5 din 4 dout 4 dout 5 switching matrix 1 2 0 3 4 5 6 7 1 2 0 3 4 5 6 7 d cha nnels to rx hdlc dchannels from tx hdlc internal bus gci1 gci0 gci1 gci0 5464-12.eps figure 11 : d, c/i and monitor channel path iii.4 - microprocessor interface iii.4.1 - description the multi-hdlc circuit can be controlledby severa types of microprocessors (st9, intel/motorola 8 or 16 data bits interfaces) such as : - st9 family - intel 80c188 8 bits - intel 80c186 16 bits - motorola 68000 16 bits during the initialization of the multi-hdlc circuit, the microprocessor interface is informedof the type of microprocessor that is connectedby polarisation of three external pins mod 0/2). two chip select (cs0/1)pins are provided.cs0 will select the internal registers and cs1 the external memory. table 14 : microprocessor interface selection mod2 pin mod1 pin mod0 pin microprocessor 0 1 1 80c188 1 1 1 80c186 1 0 0 68000 0 0 0 reserved 001 st9 iii.4.2 - definition of the interface for the differ- ent microprocessors the signals connected to the microprocessor inter- face are presented on the following figures for the different microprocessor (see figures 12, 13, 14, 15, 16 and 17 on pages 29-30). STLC5464 28/83
iii - functional description (continued) m pst9 iintel motorola 8/16 bits multi-hdlc inte rnal bus bus arbitration m p inter face multiplex address/da ta bus address bus data bus ram inter face static or dynamic ram (organize d by 16 bits) 5464-13.eps figure 12 : multi-hdlc connected to m p with multiplexed buses multi-hdlc internal bus bus arbitration address bus data bus ram interface static or dynamic ram (organized by 16 bits) m p iintel motorola 8/16 bits m p interface address bus data bus 5464-14.eps figure 13 : multi-hdlc connected to m p with non-multiplexed buses int0/1 wdo nreset cs0/1 ar dy nwr nr d ale a8/19 ad0 /7 intel 80c188 m p interface 5464-15.eps figure 14 : microprocessor interface for intel 80c188 int0/1 wdo nreset cs0/1 ar dy nwr nr d ale a16/19 ad0/15 intel 80c186 m p interface nbhe 5464-16.eps figure 15 : microprocessor interface for intel 80c186 STLC5464 29/83
iii - functional description (continued) int0/1 wdo nreset cs0/1 r/nw nuds nlds nas a1/23 ad0/15 motorola 68000 m p interface ndtack 5464-15.eps figure 16 : microprocessor interface for motorola 68000 int0/1 wdo nre s et cs0/1 wait r/nw nds nas a8/15 ad0 /7 st9 m p interface 5464-19.eps figure 17 : microprocessor interface for st9 STLC5464 30/83
iii.5 - memory interface iii.5.1 - function description the memory interface allows the connection of static or dynamic ram. the memory space ad- dressable in the two configurationsis not the same. in the case of dynamic memory (dram), the mem- ory interface will address up to 16 megabytes. in caseof staticmemory(sram) only 1 megabytewill be addressed. the memory location is always or- ganized in 16 bits. the memory is shared between the multi-hdlc and the microprocessor. theaccess to the memory is arbitrated by an internal function of the circuit: the bus arbitration. iii.5.2 - choice of memory versus microproc- essor and capacity required the memory interface depends on the memory chips which are connected. as the memory chips will be chosen versus the microprocessor and the wanted memory space, the table 22 presents the different configurations. example 1 : if the applicationrequires 16 bit mproc- essor and 1 megaword shared memory size, three capabilities are offered : - 4 dram circuits (256kx16) or - 4 dram circuits (1mx4) or - 1 dram circuit (1mx16). example 2 : if the application requires 8 bit mproc- essor and 1 megabyte shared memory size, three capabilities are offered: - 2 dram circuits (256kx16) or - 8 sram circuits (128kx8) or - 2 sram circuits (512kx8). example 3 : for small applications it is possible to connect 2 sram circuits (128kx8) to obtain 256 kilobytes shared memory. iii.5.3 - memory cycle for sram and dram, the different cycles are programmable (see paragraph omemory interface configuration register micr (32)ho on page 71). each cycle is equal to : p x 1/f with f the frequencyof signal applied to the crystal 1 input and p selected by the user. iii - functional description (continued) table 22 : dram and sdram selection versus m p microprocessor and shared memory shared memory size required by the application 8 bits m processor number of megabytes 0.5 1 2 4 8 16 16 bits m processor number of megawords 0.25 0.5 1 2 4 8 dram circuits proposed capacity organization 4 megabits 256kx16 1(256kx16) 2(256kx16) 4(256kx16) 1mx4 4(1mx4) 8(1mx4) 16(1mx4) 16 megabits 1mx16 1(1mx16) 2(1mx16) 4(1mx16) 4mx4 4(4mx4) 8(4mx4) 64 megabits 4mx16 1(4mx16) 2(4mx16) sram circuits proposed not possible capacity organization 1 megabits 128kx8 4(128kx8) 8(128kx8) 4 megabits 512kx8 2(512kx8) STLC5464 31/83
iii - functional description (continued) 1 nce1 0 nce0 dm8/15 dm0/7 512k x 16 512k x 8 5464-21.eps figure 19 : 512k x 8 sram circuit memory organization 7 nce 7 5 nce 5 1 nce 1 3 nce 3 6 nce 6 4 nce 4 0 nce 0 2 nce 2 dm8/15 dm0/7 128k x 16 128k x 8 5464-20.eps figure 18 : 128k x 8 sram circuit memory organization 7 ras3 5 ras2 1 ras0 3 ras1 6 4 0 2 dm8/15 dm0/7 256k x 16 cas1 cas0 adm0/8, nwe, noe a re conne cte d to e a ch circuit. 5464-22.eps figure 20 : 256k x 16 dram circuit organization iii.5.4 - sram interface signals a19 a18 a0 or equiv. nce7 1 1 1 nce6 1 1 0 nce5 1 0 1 nce4 1 0 0 nce3 0 1 1 nce2 0 1 0 nce1 0 0 1 nce0 0 0 0 the sram space achieves 1 mbyte max. it is always organized in 16 bits. the structure of the memory plane is shown in the following figures. because of the different chips usable, 19 address wires and 8 nce (chip enable) are necessary to address the 1 mbyte. the nce selects the most or least significant byte versus the value of a0 deliv- ered by the m p and the location of chip in the memory space. iii.5.4.1 - 18k x n sram the address bits delivered by the multi-hdlc for 128k x n sram circuits are : adm0/14 and adm15/16 (17 bits) corresponding with a1/17 delivered by the m p. iii.5.4.2 - 512k x n sram signals a0 or equiv. nce1 1 nce0 0 the address bits delivered by the multi-hdlc for 512k x n sram circuits are : adm0/14 and adm15/18 (19 bits) corresponding with a1/19 delivered by the m p. iii.5.5 - dram interface in dram, the memory space can achieve up to 16 megabytes organized by 16 bits. eleven address wires, four nras and two ncas are needed to select any byte in the memory. one nras signal selects 1 bank of 4 and the ncas signals select the bytes concerned by the transfer (1 or 2 selecting a byte or a word). the dram memory interface is then defined. the oras onlyo refresh cycles will refresh all memory locations. the refresh is pro- grammable. the frequency of the refresh is fixed by the memory requirements. iii.5.5.1 - 256k x n dram signals signals a20 a19 a0 or equiv. nras3 1 1 nras2 1 0 nras1 0 1 nras0 0 0 ncas1 1 ncas0 0 the address bits delivered by the multi-hdlc for 256k x n dram circuits are : adm0/8 (2 x 9 = 18 bits) corresponding with a1/18 delivered by the m p. STLC5464 32/83
iii - functional description (continued) 1 nras0 3 nras1 0 2 dm8/15 dm0/7 4m x 16 ncas 1 ncas 0 adm0/10, nwe, noe a re conne cte d to e a ch circuit 5464-24.eps figure 22 : 4m x 16 dram circuit organization 7 nras3 5 nras2 1 nras0 3 nras1 6 4 0 2 dm8/15 dm0/7 1m x 16 ncas1 ncas0 adm0/9, nwe, noe a re c onnected to each c ircuit 5464-23.eps figure 21 : 1m x 16 dram circuit organization m p mhdlc 0 ram m p bus rambus tro tri mhdlc 1 tro tri mhdlc n tro tri 5464-25.eps figure 23 : chain of n multi-hdlc components iii.5.5.2 - 1m x n dram signals signals a22 a20 a0 or equiv. nras3 1 1 nras2 1 0 nras1 0 1 nras0 0 0 ncas1 1 ncas0 0 the address bits delivered by the multi-hdlc for 1m x n dram circuits are : adm0/9 (2 x 10 = 18 bits) correspondingwith a1/20 delivered by the m p. iii.5.5.3 - 4m x n dram signals signals a23 a0 or equiv. nras1 1 nras0 0 ncas1 1 ncas0 0 the address bits delivered by the multi-hdlc for 4m x n dram circuits are : adm0/10 (2 x 11 = 22 bits) corresponding with a1/22 delivered by the m p. iii.6 - bus arbitration the bus arbitration function arbitrates the access to the bus between different entities of the circuit. those entities which can call for the bus are the following : - the receive dma controller, - the microprocessor, - the transmit dma controller, - the interrupt controller, - the memory interface for refreshing the dram. this list gives the memory access priorities per default. if the treatment of more than 32 hdlc channels is required by the application, it is possible to chain several multi-hdlc components.that is done with two external pins (tri, tro) and a token ring system. the tri, tro signals are managed by the bus arbitration function too. when a chip has finished its tasks, it sends a pulse of 30 ns to the next chip. STLC5464 33/83
iii - functional description (continued) iii.7 - clock selection and time synchronization iii.7.1 - clock distribution selection and supervision two clock distributions are available : clock at 4.096mhzor 8.192mhz and a synchronization sig- nal at 8khz. the component has to select one of these two distributions and to check its integrity (see figure 25 and paragraph ogeneral configura- tion register gcr (02)ho on page 57). dclk, fscgci and fscv* are output on three external pins of the multi-hdlc . dclk is the clock selected between clock a and clock b. fscgci and fscv* are functions of the selected distribu- tion and respect the gci and v* frame synchroni- zation specifications. the supervision of the clock distribution consists of verifying its availability. the detection of the clock absence is done in less than 250 m s. in case the clock is absent, an interrupt is generated with a 4khz recurrence. then the clock distribution is switched by the microprocessor. this change of clock occurs on a falling edge of the new selected distribution. depending on the applications, three different sig- nals of synchronization (gci, v* or sy) can be provided to the component. the clock a/b fre- quency can be a 4096 or 8192khz clock. the component is informed of the synchronization and clocks that are connected by software.the timings of the different synchronization are given page 38. iii.7.2 - vcxo frequency synchronization an external vcxo can be used to provide a clock to the transmission components. this clock is con- trolled by the main clock distribution (clock a or clock b at 4096khz). as the clock of the transmis- sion component is 15360 or 16384khz,a configur- able function is necessary. the vcxo frequency is divided by p (30 or 32) to provide a common sub-multiple (512khz) of the reference frequency clocka or clockb (4096khz). the comparison of these two signals gives an error signal which commands the vcxo. two external pins are needed to perform this func- tion : vcxo-in and vcxo-out (see figure 26 on page 35). clock b frame b clock a fscv* fs cgci dclk to the interna l mhdlc frame clock ref. clock res et int1 hcl clock s upervision de a ctivation (cs d) aor b selected (bs el) select aor b (s elb) clock s election at res et frame a a nd clock a a re s elected clock lack de te ction from 250 m s clock adap tation syn0 s yn1 general configuration register (gcr) frame a 5464-26.eps figure 24 : mhdlc clock generation STLC5464 34/83
iii - functional description (continued) /p /8 low p ass f ilter vcxo f = 15360khz or 16384khz vcxo in vcxo out evm mhdlc ref = 4096khz if f = 153 60khz, p = 30 if f = 163 84khz, p = 32 oux 8 7 5464-27.eps figure 25 : vcxo frequency synchronization iii.8 - interrupt controller iii.8.1 - description three external pins are used to manage the inter- rupts generated by the multi-hdlc . the interrupts have three main sources : - the operating interrupts generated by the hdlc receivers/transmitters, the ci receivers and the monitor transmitters/receivers. int0 pin is re- served for this use. - the interrupt generatedby an abnormal working of theclockdistribution.int1pinisreservedforthisuse. - the non-activity of the microprocessor (watch- dog). wdo pin is reserved for this use. iii.8.2 - operating interrupts (int0 pin) there are five main sources of operating interrupts in the multi-hdlc circuit : - the hdlc receiver, - the hdlc transmitter, - the ci receiver, - the monitor receiver, - the monitor transmitter. when an interrupt is generated by one of these functions, the interrupt controller : - collects all the information about the reasons of this interrupt, - stores them in external memory, - informs the microprocessor by positioning the int0 pin in the high level. three interrupt queues are built in external memory to store the information about the interrupts : - a single queue for the hdlc receivers and trans- mitters, - one for the ci receivers, - one for the monitor receivers. the microprocessor takes the interrupts into ac- count by reading the interrupt register (ir) of the interrupt controller. this register informs the microprocessor of the interrupt source. the microprocessor will have in- formation about the interruptsource by readingthe corresponding interrupt queue (see paragraph oin- terrupt register ir (38) h o on page 74). on an overflow of the circular interrupt queues and an overrun or underrun of the different fifo, the int0 pin is activated and the origin of the interrupt is stored in the interrupt register. a 16 bits register is associated with the tx monitor interrupt. it informs the microprocessor of which transmitter has generated the interrupt (see para- graph otransmit monitor interrupt register tmir (30) h o on page 71). iii.8.3 - time base interrupts (int1 pin) the time base interrupt is generated when an absence or an abnormal working of clock distribu- tion is detected. the int1 pin is activated. iii.8.4 - emergency interrupts (wdo pin) the wdo signal is activated by an overflow of the watchdog register. iii.8.5 - interrupt queues there are three different interrupt queues : - tx and rx hdlc interrupt queue, - rx c/i interrupt queue, - rx monitor interrupt queue. their length can be defined by software. for debugging function, each interrupt word of the ci interruptqueue and monitor interrupt queue can be followed by a timestamped word. it is composed of a counter which runs in the range of 250 m s. the counter is the same as the watchdog counter. consequently,the watchdog functionisn't available at the same time. STLC5464 35/83
iii - functional description (continued) initialization bloc k hdlc (tx a nd rx) inter rupt queue mon (rx) inter rup tqueue c/i (rx) inter rup t queue iba iba + 254 iba + 256 iba + 256 + hdlc que ue size iba + 256 + hdlc que ue s ize + mon que ue s ize 5464-28.eps figure 26 : the three circular interrupt memories iii.9 - watchdog this function is used to control the activity of the application. it is composed of a counter which counts down from an initial value loaded in the timer register by the microprocessor. if the microprocessor doesn't reset this counter before it is totally decremented, the external pin wdo is activated ; this signal can be used to reset the microprocessor and all the application. the initial time value of the counter is programma- ble from 0 to 15s in increments of 0.25ms. at the reset of the component, the counter is auto- matically initialized by the value corresponding to 512ms which are indicated in the timer register. the microprocessor must put wdr (idcr regis- ter) too1o to reset this counter and to confirm that the application started correctly. in the reverse case, the wdo signal could be used to reset the board a second time. iii.10 - reset there are two possibilities to reset the circuit : - by software, - by hardware. each programmable register receives its default value. after that, the default value of each data register is stored in the associated memory except for time slot assigner memory. STLC5464 36/83
iv - dc specifications absolute maximum ratings symbol parameter value unit v dd 5v power supply voltage -0.5, 6.5 v input or output voltage -0.5, v dd + 0.5 v t stg storage temperature -55, +125 c power dissipation symbol parameter test conditions min. typ. max. unit p power consumption v dd = 5v 400 mw recommended dc operating conditions symbol parameter test conditions min. typ. max. unit v dd 5v power supply voltage 4.75 5.25 v t oper operating temperature 0 +70 c note 1 : all the following specifications are valid only within these recommended operating conditions. ttl input dc electrical characteristics symbol parameter test conditions min. typ. max. unit v il low level input voltage 0.8 v v ih high level input voltage 2.0 v i il low level input current v i =0v 1 m a i ih high level input v i =v dd -1 m a vhyst schmitttrigger hysteresis 0.4 0.7 1 v vt+ positive trigger voltage 2 2.4 v vt- negative trigger voltage 0.6 0.8 v c in input capacitance (see note 2) f = 1mhz @ 0v 2 4 pf c out output capacitance 4 c i/o bidirextional i/o capacitance 4 8 note 2 : excluding package cmos output dc electrical characteristics symbol parameter test conditions min. typ. max. unit v ol low level output voltage i ol = x ma (see note 3) 0.4 v v oh high level output voltage i oh = -x ma (see note 3) v dd5 -0.4 v note 3 : x is the source/sink current under worst case conditions and is reflected in the name of the i/o cell according to the drive capability. x = 4 or 8ma. protection symbol parameter test conditions min. typ. max. unit vesd electrostatic protection c = 100pf, r = 1.5k w 2000 v STLC5464 37/83
v - clock timing v.1 - synchronization signals delivered by the system for one of three different input synchronizations which is programmed, fscg and fscv* signals delivered by the multi-hdlc are in accordance with the figure hereafter. t5h t2 t5l 45 36701 t1 bit4 bit5 bit0 bit1 bit6 bit7 bit3 time s lot 31 time s lot 0 t4 t3 t4 t3 t3 t4 cgi clock b clock a 1) s y mode f ra me a (or b) 2) gcimode f ra me a (or b) 3) v*mod e f ra me a (or b) din 0/8, echo do ut 0/7, cb iffs = fscg tdm0/7 fscg delivere d by the circuit fscv* de livere d by the circuit the four multiplex configura tion registers are a t zero (no de lay). 5464-29.eps figure 27 : clocks received and delivered by the multi-hdlc symbol parameter min. typ. max. unit t1 clock period if 4096khz clock period if 8192khz 239 120 244 122 249 125 ns ns t2 delay between clock a and clock b - 60 0 +60 ns t3 set up time frame a (or b)/clock a (or b) 10 t1-10 ns t4 t4gci hold time frame a (or b)/clock a (or b) 10 10 t1-10 125000 - (t1 - 10) ns t5 clock ratio t5h/t5l 75 100 125 % STLC5464 38/83
v - clock timing (continued) v.2 - tdm synchronization t1 t3 bit 0, time slot 0 t7 t7 dclk de live re d by the multi-hdlc fscg d e livere d by the multi-hdlc dout0/7, cb din0/8 the four multiplex configura tion re giste rs a re a t z e ro (no d e lay be twe e n fs a nd multiplexe s). t8 clock a (o r b) t4 t2 t5 bit 7, time s lot 31 echo t9 t6 5464-30.eps figure 28 : synchronization signals received by the multi-hdlc symbol parameter min. typ. max. unit t1 clock period if 4096khz clock period if 2048khz id clocka or b 244 488 id clocka or b ns ns t2 delay between clock a or b and dclk (30pf) 5 30 ns t3 set-up time fs/dclk 20 t1-20 ns t4 hold time fs/dclk 20 ns t5 duration fs 244 125000-244 ns t6 dclk to data 50pf dclk to data 100pf 50 100 ns t7 set-up time data/dclk 20 ns t7 hold time data/dclk 20 ns t8 set-up echo/dclk (rising edge) 155 ns t9 hold time echo/dclk (rising edge) 205 ns STLC5464 39/83
v - clock timing (continued) v.3 - gci interface ch0 ch1 ch7 b1 b2 mon d c/i ae 125 m s t1 t3 bit 0, time s lot 0 t3 t7 t7 fs re ce ived by the multi-hdlc din4/5 dout4/5 dclk de livered by the multi-hdlc fscg de livered by the multi-hdlc dout0/7, cb iffscg is connected to fs din0/8 the four multiplex configura tion registers a re a t ze ro (no de lay betwee n fs and multiplexes ). t6 gci channel 5464-31.eps figure 29 : gci synchro signal delivered by the multi-hdlc symbol parameter min. typ. max. unit t1 clock period if 4096khz clock period if 2048khz clocka/b tmin 244 488 clocka/b tmax ns ns t3 dclk to fscg 20 ns t5 duration fs 244 125000-244 ns t6 dclk to data 50pf dclk to data 100pf 50 100 ns ns t7 set-up time data/dclk 20 ns t7 hold time data/dclk 20 ns STLC5464 40/83
v - clock timing (continued) v.4 - v* interface ch0 ch1 ch7 b1 b2 mon d c/i at 125 m s t1 t3 bit 3, time s lot 31 t3 t7 t7 fs re ce ived by th e multi-hdlc din4/5 dout4/5 dclk de livere d by th e multi-hdlc fscv* delivered by th e multi-hdlc dout0/7, cb iffscg is connecte d to fs din0/8 th e four multiple x configura tion re giste rs a re a t z e ro (no de la y be twe e n fs a nd multiple xe s ). gci channel 5464-32.eps figure 30 : v* synchronization signal delivered by the multi-hdlc symbol parameter min. typ. max. unit t1 clock period 4096khz 244 ns t3 dclk to fscv* 20 ns t5 duration fscv* 244 ns t6 clock to data 50pf clock to data 100pf 50 100 ns ns t7 set-up time data/dclk 20 ns t7 hold time data/dclk 20 ns STLC5464 41/83
vi - memory timing t total read cycle tu hz hz hz hz e ach s ignal from the mhdlc is high impe dance outside this time if mbl = 0 a a a 1/f nds fro m m p (or e quivalent) masterclock a pplied to xtal1 p in adm0/10 nwe noe dm0/15 from dram circuit note : see mbl de finition a a a nras 0/3 tv ncas 0/1 tw tz tv/2 ts tw + tz /2 th 5464-33.eps figure 31 : dynamic memory read signals from the multi-hdlc vi.1 - dynamic memories symbol parameter min. typ. max. unit t delay between data strobe from the mp and beginning of cycle 2/f a delay between masterclock and edge of each signal delivered by the mhdlc (30pf) 20 ns tw delay between ncas falling edge and ncas rising edge 1/f 2/f ns tz delay between ncas rising edge and end of cycle 1/f 2/f ns ts set-up time data /ncas rising edge 20 ns th hold time data/ncas rising edge 0 ns STLC5464 42/83
vi - memory timing (continued) t tota l write cycle tu hz hz hz hz ea ch s ignal from the mhdlc is high impe dance outside this time if mbl = 0 a a a 1/f nds fro m m p (or equivalent) maste rclock a pplied to xtal1 p in adm0/10 nwe noe dm0/15 no te : s e e mbl definition a a a nras 0/3 tv ncas 0/1 tw tz tv/2 td 5464-34.eps figure 32 : dynamic memory write signals from the multi-hdlc symbol parameter min. typ. max. unit 1/f f : masterclock frequency 32 33 mhz tu delay between beginning of cycle and nras falling edge 1/f 2/f ns tv delay between nras falling edge and ncas falling edge 1/f 2/f ns tw delay between ncas falling edge and nwe rising edge 1/f 2/f ns tz delay between nwe rising edge and end of cycle 1/f 2/f ns tv/2 delay between nras falling edge and address change 1/2f 1/f ns td data valid after beginning of cycle (30 pf) 1/f 1/f ns note : total cycle : tu + tv + tw + tz STLC5464 43/83
t tota l rea d cycle twz ts th hz hz hz hz each s igna l de livere d by the mhdlc is high impeda nce outside this time a a a a 1/f nds fro m m p (or equivalent) masterclock applied to xtal1 p in adm0/18 nce0/7 nwe noe dm0/15 from s ram circuit note : see mbl de finition 5464-35.eps figure 33 : static memory read signals from the multi-hdlc vi - memory timing (continued) vi.2 - static memories symbol parameter min. typ. max. unit t delay between data strobe delivered by the mp and beginning of cycle 2/f 1/f f: masterclock frequency total read cycle: twz + 1/f a delay between masterclock and edge of each signal delivered by the mhdlc (30pf) 20 ns twz noe width 1/f 4/f ns ts set-up time data /noe rising edge 20 ns th hold time data /noe rising edge 0 1/f ns STLC5464 44/83
t total write cycle tuv hz hz hz hz each signal delivered by the mhdlc is high impedance outside this time a a a a 1/f nds from m p (or equivalent) masterclock applied to xtal1 pin adm0/18 nce0/7 nwe noe dm0/15 note : see mbl definition a 5464-36.eps figure 34 : static memory write signals from the multi-hdlc vi - memory timing (continued) symbol parameter min. typ. max. unit t delay between data strobe delivered by the m p and beginning of cycle 2/f 1/f f : masterclock frequency a delay between masterclock and edge of each signal delivered by the mhdlc (30pf) 20 ns tuv nce width 1/f 4/f ns note : total write cycle : tuv + 1/f STLC5464 45/83
ncs0/1 ready nas/ ale nds/ nrd ad0/7 r/w / nwr t6 t5 t7 t8 t12 t4 t3 t1 t2 d0/7 a0/7 t11 t9 t10 5464-37.eps figure 35 : st9 read cycle vii - microprocessor timing vii.1 - st9 family mod0=1, mod1=0, mod2=0 symbol parameter min. typ. max. unit t1 delay ready / chip select (if t3 > t1), (30pf) 0 30 ns t2 hold time chip select /data strobe 14 ns t3 delay ready / nas (if t1 > t3), (30pf) 0 30 ns t4 width nas 20 ns t5 set-up time address / nas 9 ns t6 hold time address / nas 9 ns t7 data valid before ready 0 ns t8 data valid after data strobe (30pf) 0 ns t9 set-up time r/w /nas 15 ns t10 hold time r/w / data strobe 15 ns t11 width nds when immediate access 50 ns t12 delay nds / ncs 5 ns STLC5464 46/83
ncs0/1 ready nas/ ale nds/ nrd ad0/7 r/w / nwr t6 t5 t7 t8 t12 t4 t3 t1 t2 d0/7 a0/7 t11 t10 t9 5464-38.eps figure 36 : st9 write cycle vii - microprocessor timing (continued) symbol parameter min. typ. max. unit t1 delay ready / chip select (if t3 > t1), (30pf) 0 30 ns t2 hold time chip select / data strobe 14 ns t3 delay ready / nas (if t1 > t3), (30pf) 0 30 ns t4 width nas 20 ns t5 set-up time address / nas 9 ns t6 hold time address / nas 9 ns t7 set-up time data / data strobe -15 ns t8 hold time data / data strobe 15 ns t9 set-up time r/w / nas 15 ns t10 hold time r/w / data strobe 15 ns t11 width nds when immediate access 50 ns t12 delay nds / ncs 5 ns STLC5464 47/83
ncs0/1 ready nas /ale nds /nrd ad0/7 r/w / nwr t6 t5 t7 t8 t12 t4 t3 t1 t2 d0/7 a0/7 5464-39.eps figure 37 : 80c188 read cycle vii - microprocessor timing (continued) vii.2 - 80c188 mod0=1, mod1=1, mod2=0 symbol parameter min. typ. max. unit t1 delay ready / chip select (if t3 > t1), (30pf) 0 20 ns t2 hold time chip select / nrd 10 ns t3 delay ready / ale (if t1 > t3), (30pf) 0 20 ns t4 width ale 20 ns t5 set-up time address / ale 5 ns t6 hold time address / ale 5 ns t7 data valid before ready 0 ns t8 data valid after nrd (30pf) 0 ns t12 delay nds / ncs 0 ns STLC5464 48/83
ncs0/1 ready nas /ale nds /nrd ad0/7 r/w / nwr t6 t5 t7 t8 t12 t4 t3 t1 t2 d0/7 a0/7 5464-40.eps figure 38 : 80c188 write cycle vii - microprocessor timing (continued) symbol parameter min. typ. max. unit t1 delay ready / chip select (if t3 > t1), (30pf) 0 20 ns t2 hold time chip select / nwr 10 ns t3 delay ready / ale (if t1 > t3), (30pf) 0 20 ns t4 width ale 20 ns t5 set-up time address / ale 5 ns t6 hold time address / ale 5 ns t7 set-up time data / nwr -15 ns t8 hold time data / nwr 15 ns t12 delay nwr / ncs 0 ns STLC5464 49/83
ncs0/1 ready nas /ale nds /nrd ad0/15 r/w / nwr nbhe a16/19 t6 t10 t5 t9 t11 t7 t8 t12 t4 t3 t1 t2 d0/15 nbhe nbhe a16/19 a0/15 5464-41.eps figure 39 : 80c186 read cycle vii - microprocessor timing (continued) vii.3 - 80c186 mod0=1, mod1=1, mod2=1 symbol parameter min. typ. max. unit t1 delay ready / chip select (if t3 > t1), (30pf) 0 20 ns t2 hold time chip select / nrd 10 ns t3 delay ready / ale (if t1 > t3), (30pf) 0 20 ns t4 width ale 20 ns t5 set-up time address / ale 5 ns t6 hold time address / ale 5 ns t7 data valid before ready -15 ns t8 data valid after nrd (30pf) 0 ns t9 set-up time nbhe-address a16/19 / ale 5 ns t10 hold time address a1619 / nrd 10 ns t11 hold time nbhe- / nrd 10 ns t12 delay nrd / ncs 0 ns STLC5464 50/83
symbol parameter min. typ. max. unit t1 delay ready / chip select (if t3 > t1), (30pf) 0 20 ns t2 hold time chip select / nwr 10 ns t3 delay ready / ale (if t1 > t3), (30pf) 0 20 ns t4 width ale 20 ns t5 set-up time address / ale 5 ns t6 hold time address / ale 5 ns t7 set-up time data / nwr -15 ns t8 hold time data / nwr 15 ns t9 set-up time nbhe-address a16/19 / ale 5 ns t10 hold time address 16/19 / ale 10 ns t11 hold time nbhe- / nwr 10 ns t12 delay nwr / ncs 0 ns vii - microprocessor timing (continued) ncs0/1 ready nas /ale nds /nrd ad0/15 r/w / nwr nbhe a16/19 t6 t10 t5 t9 t11 t7 t8 t12 t4 t3 t1 t2 d0/15 nbhe nbhe a16/19 a0/15 5464-42.eps figure 40 : 80c186 write cycle STLC5464 51/83
vii.4 - 68000 mod0=0, mod1=0, mod2=1 symbol parameter min. typ. max. unit t1 delay ndtack / ncs0/1 (if t3 > t1), (30pf) delay when immediate access 0 30 ns ns t2 hold time chip select / nlds-nuds 14 ns t3 delay ndtack / nlds-nuds falling edge (if t1> t3), (30pf) delay when immediate access 0 30 ns ns t4 delay ndtack / nlds-nuds rising edge 0 30 ns t5 set-up time address / nas 9 ns t6 hold time address / nlds-nuds 9 ns t7 data valid before ndtack falling edge (30pf) 0 ns t8 data valid after nlds-nuds rising edge (30pf) 0 ns t12 delay nds / ncs 0 ns t7 t5 t6 t8 t3 t1 t2 t4 t12 ncs0/1 ndtack nas/ ale size0 /nlds size1 /nuds a1/23 r/w / nwr d0/15 a1/23 5464-43.eps figure 41 : 68000 read cycle vii - microprocessor timing (continued) STLC5464 52/83
symbol parameter min. typ. max. unit t1 delay ndtack / ncs0/1 (if t3 > t1), (30pf) delay when immediate access 0 30 ns ns t2 hold time chip select / nlds-nuds 14 ns t3 delay ndtack / nlds-nuds falling edge (if t1> t3), (30pf) delay when immediate access 0 30 ns ns t4 delay ndtack / nlds-nuds rising edge ns t5 set-up time address / nas 9 ns t6 hold time address / nlds-nuds 9 ns t9 set-up time data / nlds-nuds 15 ns t10 hold time data / nlds-nuds 15 ns t12 delay nds / ncs 0 ns t5 t6 t3 t1 t2 t4 t12 ncs0/1 ndtack nas/ ale size0 /nlds size1 /nuds a1/23 r/w / nwr d0/15 a1/23 t9 t10 5464-44.eps figure 42 : 68000 write cycle vii - microprocessor timing (continued) STLC5464 53/83
vii - microprocessor timing (continued) 1/f a t s t h tro tri master c loc k (applied to xtal1 p in) a 5464-47.eps figure 43 : token ring vii.5 - token ring timing symbol parameter min. typ. max. unit 1/f f : masterclock frequency 32.768 mhz a delay between masterclock rising edge and edges of tro pulse delivered by the mhdlc (10pf) 25 ns t s set-up time tri/masterclock masterclock falling edge 5 ns t h hold time tri/masterclock falling edge 5 0 ns vii.6 - master clock timing symbol parameter min. typ. max. unit f masterclock frequency 30 32.768 33 mhz 1/f masterclock period 30.3 30.5 33.3 ns th masterclock high 12 ns tl masterclock low 12 ns 1/f t h t l master clock (applied to xtal1 pin) 5464-48.eps figure 44 : master clock STLC5464 54/83
viii - internal registers `not used' bits (nu) are accessible by the microprocessor but the use of these bits by software is not recommended. `reserved' bits are not implemented in the circuit. however, it is not recommended to use this address. viii.1 - identification and dynamic command register - idcr (00)h bit15 bit8 bit7 bit 0 c15 c14 c13 c12 c11 c10 c9 c8 c7 c6 c5 c4 c3 c2 c1 c0 when this register is read by the microprocessor, the circuit code c0/15 is returned. reset has no effect on this register. c0/3 indicates the version. c4/7 indicates the revision. c8/11 indicates the foundry. c12/15 indicates the type. example : this code is (0010)h for the first sample. when this register is written by the microprocessor then : bit15 bit8 bit7 bit 0 nu nu nu nu nu nu nu nu nu nu nu nu nu rss wdr tl tl : token launch when tl is set to 1 by the microprocessor, the token pulse is launched from the tro pin (token ring output pin). this pulse is provided to the tri pin (token ring input pin) of the next circuit in the applications where several multi-hdlc s are connected to the same shared memory. wdr : watchdog reset. when the bit 1 (wdr) of this register is set to 1 by the microprocessor, the watchdog counter is reset. rss : reset software when the bit 2 (rss) of this register is set to 1 by the microprocessor, the circuit is reset (same action as reset pin). after writing this register, the values of these three bits return to the default value. viii.2 - general configuration - gcr (02)h bit15 bit8 bit7 bit 0 nu mbl afab scl bsel selb csd hcl syn1 syn0 d7 evm tsv trd pma wdd after reset (0000) h wdd : watch dog disable wdd = 1, the watch dog is masked : wdo pin stays at o0o. wdd = 0, the watch dog generates an o1o on wdo pin if the microprocessor has not reset the watch dog during the duration programmed in timer register. pma : priority memory access pma = 1, if the token ring has been launched it is captured and kept in order to authorize memory accesses. pma = 0, memory is accessible only if the token is present; after one memory access the token is re-launched from tro pin of the current circuit to tri pin of the next circuit. trd : token ring disable trd = 1, if the token has been launched, the token ring is stopped and destroyed ; memory accesses are not possible. the token will not appear on tro pin. trd = 0, the token ring is authorized ; when the token will be launched,it will appearon tro pin. STLC5464 55/83
tsv : time stamping validated tsv = 1, the time stamping counter becomes a free binary counter and counts down from 65535 to 0 in step of 250ms (total = 16384ms). so if an event occurs when the counter indicates a and if the next event occurs when the counter indicates b then : t = (a-b) x 250ms is the time which haspassedbetweenthe two eventswhich have beenstored in memoryby the interruptcontroller (for rx c/i and rx mon channel only). tsv = 0, the counter becomes a decimal counter.the timer register and this decimal counter constitute a watch dog or a timer. evm : external vcxo mode evm=1,vcxo synchronization counter is divided by 32. evm=0,vcxo synchronization counter is divided by 30. d7 : hdlc connected to matrix d7 = 1, the transmit hdlc is connected to matrix input 7, the din7 signal is ignored. d7 = 0, the din7 signal is taken into account by the matrix, the transmit hdlc is ignored by the matrix. syn0/1: synchronization syn0/1 : these two bits define the signal applied on framea/b inputs. for more details, see osynchronization signals delivered by the system. 7.1. syn1 syn0 signal applied on framea/b inputs 0 0 syiinterface 0 1 gci interface (the signal defines the first bit of the frame) 1 0 vstar interface (the signal defines thrid bit of the frame) 1 1 not used hcl : high bit clock this bit defines the signal applied on clocka/b inputs. hcl = 1, bit clock signal is at 8192khz hcl= 0, bit clock signal is at 4096khz csd : clock supervision deactivation csd = 1, the lack of selected clock is not seen by the microprocessor; int1 is masked. csd = 0, when the selected clock disappears the int1 pin goes to 5v, 250ms after this disappearance. selb : select b selb = 1, frame b and clock b must be selected. selb = 0, frame a and clock a must be selected. bsel : b selected (this bit is read only) bsel = 1, frame b and clock b are selected. bsel = 0, frame a and clock a are selected. scl : single clock this bit defines the signal delivered by dclk output pin. scl = 1, data clock is at 2048khz. scl = 0, data clock is at 4096khz. afab : advanced frame a/b signal afab = 1, the advance of frame a signal and frame b signal is 0.5 bit time versus the signal frame a (or b) drawn in figure 27. afab = 0, frame a signal and frame b signal are in accordance with the clock timing (see : synchronization signals delivered by the figure 27). viii - internal registers (continued) STLC5464 56/83
mbl : memory bus low impedance mbl = 1, the shared memory bus is at low impedance between two memory cycles. the memory bus includes control bits, data bits, address bits. one multi-hdlc is connected to the shared memory. mbl = 0, the shared memory bus is at high impedance between two memory cycles. several muti-hdlcs can be connected to the shared memory. one pull up resistor is recommended on each wire. viii.3 - input multiplex configuration register 0 - imcr0 (04)h bit15 bit8 bit7 bit 0 lp3 del3 st(3)1 st(3)0 lp2 del2 st(2)1 st(2)0 lp1 del1 st(1)1 st(1)0 lp0 del0 st(0)1 st(0)0 after reset (0000) h see definition in next paragraph. viii.4 - input multiplex configuration register 1 - imcr1 (06)h bit15 bit8 bit7 bit 0 lp7 del7 st(7)1 st(7)0 lp6 del6 st(6)1 st(6)0 lp5 del5 st(5)1 st(5)0 lp4 del4 st(4)1 st(4)0 after reset (0000) h st(i)0 : step0 for each input multiplex i(0 i 7), delayed or not. st(i)1 : step1 for each input multiplex i(0 i 7), delayed or not. del(i); : delayed multiplex i(0 i 7). del (i) st (i) 1 st (i) 2 step for each input multiplex 0/7 delayed or not x 0 0 each received bit is sampled at 3/4 bit-time without delay. first bit of the frame is defined by frame synchronization signal. 1 0 1 each received bit is sampled with 1/2 bit-time delay. 1 1 0 each received bit is sampled with 1 bit-time delay. 1 1 1 each received bit is sampled with 2 bit-time delay. 0 0 1 each received bit is sampled with 1/2 bit-time advance. 0 1 0 each received bit is sampled with 1 bit-time advance 0 1 1 each received bit is sampled with 2 bit-time advance. when imtd = 0 (bit of smcr), del = 1 is not taken into account by the circuit. lp (i) : loopback 0/7 lpi = 1, output multiplex i is put instead of input multiplex i (0 i 7). loopbackis transparent or not in accordance with omvi (bit of output multiplex configuration register). lpi = 0, normal case, input multiplex i(0 i 7) is taken into account. n.b. if din4 and din5 are gci multiplexes : then st(4)1 = st(4)0 = 0 and st(5)1 = st(5)0 = 0 normally. viii.5 - output multiplex configuration register 0 - omcr0 (08)h bit15 bit8 bit7 bit 0 omv3 del3 st(3)1 st(3)0 omv2 del2 st(2)1 st(2)0 omv1 del1 st(1)1 st(1)0 omv0 del0 st(0)1 st(0)0 after reset (0000) h see definition in next paragraph. viii - internal registers (continued) STLC5464 57/83
viii.6 - output multiplex configuration register 1 - omcr1 (0a)h bit15 bit8 bit7 bit 0 omv7 del7 st(7)1 st(7)0 omv6 del6 st(6)1 st(6)0 omv5 del5 st(5)1 st(5)0 omv4 del4 st(4)1 st(4)0 after reset (0000) h st(i)0 : step0 for each output multiplex i(0 i 7), delayed or not. st(i)1 : step1 for each output multiplex i(0 i 7), delayed or not. del(i); : delayed multiplex i(0 i 7). del (i) st (i) 1 st (i) 2 step for each output multiplex 0/7 delayed or not x 0 0 each bit is transmitted on the rising edge of the double clock without delay. bit 0 is defined by frame synchronization signal. 1 0 1 each bit is transmitted with 1/2 bit-time delay. 1 1 0 each bit is transmitted with 1 bit-time delay. 1 1 1 each bit is transmitted with 2 bit-time delay. 0 0 1 each bit is transmitted with 1/2 bit-time advance. 0 1 0 each bit is transmitted with 1 bit-time advance 0 1 1 each bit is transmitted with 2 bit-time advance. when imtd = 0 (bit of smcr), del = 0 is not taken into account by the circuit. omv (i) : output multiplex validated 0/7 omvi =1, condition to have douti pin active (0 i 7). omvi =0, douti pin is high impedance continuously (0 i 7). n.b. if din4 and din5 are gci multiplexes : then st(4)1 = st(4)0 = 0 and st(5)1 = st(5)0 = 0 normally. viii.7 - switching matrix configuration register - smcr (0c)h bit15 bit8 bit7 bit 0 nu nu nu nu nu nu nu nu nu me sgc sav sgv ts1 ts0 imtd after reset (0000) h imtd : increased minimum throughput delay when si = 0 (bit of cmdr, variable delay mode) : imtd = 1, the minimum delay through the matrixmemoryis three time slots whateverthe selected tdm output. imtd = 0, the minimum delay through the matrix memory is two time slots whatever the selected tdm output. ts0 : tristate 0 ts0 = 1, the dout0/3 and dout6/7 pins are tristate : o0o is at low impedance, o1o is at low impedance and the third state is high impedance. ts0 = 0, the dout0/3 and dout6/7 pins are open drain : o0o is at low impedance, o1o is at high impedance. ts1 : tristate 1 ts1 = 1, the dout4/5 pins are tristate : o0o is at low impedance, o1o is at low impedance and the third state is high impedance. ts1 = 0, the dout4/5 pins are open drain : o0o is at low impedance, o1o is at high impedance. sgv : pseudo random sequence generator validated sgv = 1,prs generator is validated.the pseudo random sequence is transmitted during the related time slot(s). sgv = 0, prs generator is reset.o0o are transmitted during the related time slot. sav : pseudo random sequence analyzer validated sav = 1, prs analyzer is validated. sav = 0, prs analyzer is reset. sgc : pseudo random sequence generator corrupted when sgc bit goes from 0 to 1, one bit of sequence transmitted is corrupted. when the corrupted bit has been transmitted, sgc bit goes from 1 to 0 automatically. viii - internal registers (continued) STLC5464 58/83
me : message enable me = 1 the contents of connection memory is output on dout0/7 continuously. me = 0 the contents of connection memory acts as an address for the data memory. nu : not used. viii.8 - connection memory data register - cmdr (0e)h control register (ctlr) source register (srcr) bit15 bit8 bit7 bit 0 nu ps prsa prsg ins otsv loop si im2 im1 im0 its 4 its 3 its 2 its 1 its 0 after reset (0000) h this 16 bit register is constituted by two registers : source register (srcr) and control register (ctlr) respectively 8 bits and 7 bits. source register (srcr) has two use modes depending on cm (part of cmar). cm = 1, access to connection memory (read or write) - prsg = 0, its 0/4 and im0/2 bits are defined hereafter : its 0/4 : input time slot 0/4 define itsx with : 0 x 31; im0/2 : input time division multiplex 0/2 define itdmp with : 0 p 7. - prsg = 1, the pseudo random sequence generator is validated, srcr is not significant. cm = 0, access to data memory (read only). src is the data register of the data memory. control register (ctlr) defines each output time slot otsy of each output time division multi- plex otdmq : si : sequence integrity si = 1, the delay is always : (31 - itsx) + 32 + otsy(constant delay). si = 0, the delay is minimum to pass through the data memory (variable delay). loop : loopback per channelrelevant if two connectionshas been established (bidirectional or not). loop = 1, otsy, otdmq is taken into account instead of itsy, itdmq. otsv = 1, transparentmode loopback. otsv = 0, not transparent mode loopback. otsv : output time slot validated otsv = 1, otsy otdmq is enabled. otsv = 0, otsy otdmq is high impedance. (otsy : output time slot with 0 y 31; otdmq : output time division multiplex with 0 q 7). ins : insert ins = 1 the transfer from prs generator or connection memory to dout0/7 is validated. ins = 0 the transfer from data memory to dout0/7 is validated. prsg : pseudo random sequence generator this bit has effect only if ins = 1. if prsg = 1, pseudo random sequence generator delivers eight bits belonging to the same sequence. hyperchannel at n x 64 kb/s is possible. if prsg = 0, connection memory delivers eight bits d0/7. prsa : pseudo random sequence analyzer if prsa = 1, prs analyzer is enabled during otsy otdmq and receives data : ins = 0, data comes from data memory. ins = 1 and prsg=1, data comes from prs generator (test mode). if prsa = 0, prs analyzer is disabled during otsy otdmq. ps : programmable synchronization if ps = 1, programmable synchronization signal pin is at o1o during the bit time defined by otsy and otdmq. for otsy and otdmq with y = q = 0, pss pin is at o1o during the first bit of the frame defined by the frame synchronization signal (fs). if ps = 0, pss pin is at o0o during the bit time defined by otsy and otdmq. viii - internal registers (continued) STLC5464 59/83
viii.9 - connection memory address register - cmar (10)h access mode register (amr) destination register (dstr) bit15 bit8 bit7 bit 0 nu nu tc cacl cac nu cm read om2 om1 om0 ots4 ots3 ots2 ots1 ots0 after reset (0800) h this 16 bit register is constituted by two registers : destinationregister (dstr) and accessmode register (amr) respectively 8 bits and 6 bits. remark : it is mandatory for this specific register to write successively : - first dstr - then amr destination register (dstr) when dstr register is written by the microprocessor, a memory access is launched. dstr has two use modes depending on cm (bit of cmar). cm = 1, access to connection memory (read or write) ; when cm = 1, ots 0/4 and om 0/2 bits are defined hereafter : ots 0/4 : output time slot 0/4 define otsy with : 0 y 31, om0/2 : output time division multiplex 0/2 define otdmq with : 0 q 7. - cac = cacl = 0, dstr is the address register of the connection memory; - cac or cacl = 1, dstr is used to indicate the current address for the connection memory ; its contents is assigned to the outputs. cm = 0, access to data memory (read only) ; - dstr is the address register of the data memory; its contents is assigned to the inputs. access mode register (amr) read : read memory read = 1, read connection memory (or data memory in accordance with cm). read = 0, write connection memory. cm : connection memory cm = 1, write or read connection memory in accordance with read. cm = 0, read only data memory (read = 0 has no effect). cac : cyclical access cac = 1 if write connection memory, an automatic data write from connection memory data register (cmdr) up to 256 locations of connectionmemory occurs. the first address is indicated by the register dstr, the last is (ff)h. if read connection memory, an automatic transfer of data from the location indicated by the register (dstr) into connection memory data register (cmdr) after reading by the microprocessor occurs. the last location is (ff)h. cac = 0, write and read connection memory in the normal way. cacl : cyclical access limited cacl = 1 if write connection memory, an automatic data write from connection memory data register (cmdr) up to 32 locations of connection memory occurs. the first location is indicated by ots 0/4bits of the register (dstr) related to otdmq as defined by om0/2 occurs. the last location is q +1 f(h). if read connection memory, an automatic transfer of data from connection memory into connection memory data register (cmdr) after reading this last by the microprocessor occurs.the first location is indicated by ots 0/4 bits of the register (dstr) related to otdmq as defined by om0/2. the last location is q +1 f(h). cacl = 0, write and read connection memory in the normal way. viii - internal registers (continued) STLC5464 60/83
tc : transparent connection tc = 1, if read = 0 : cac = 0 and cacl = 0. the dstr bits are taken into account instead of srcr bits. srcr bits are ignored (destination and source are identical). the contents of input time slot i - input multiplex j is switched into output time slot i - output multiplex j. cac = 0 and cacl = 1. up to 32 otransparent connectionso are set up. cac = 1 and cacl = 0. up to 256 otransparent connectionso are set up. tc = 0, write and read connection memory in the normal way. viii.10 - sequence fault counter register - sfcr (12)h bit15 bit8 bit7 bit 0 f15f14f13f12f11f10f9f8f7f6f5f4f3f2f1f0 after reset (0000) h this register is read only. when this register is read by the microprocessor, this register is reset (0000) h . f0/15 : fault0/15 number of faults detected by the pseudo random sequence analyzer if the analyzer has been validated and has recovered the receive sequence. when the fault counter register reaches (ffff) h it stays at its maximum value. viii.11 - time slot assigner address register - taar (14)h bit15 bit8 bit7 bit 0 ts4 ts3 ts2 ts1 ts0 read nu hdi r e s e r v e d after reset (0100) h read : read memory read = 1, read time slot assigner memory. read = 0, write time slot assigner memory. ts0/4 : time slots0/4 these five bits define one of 32 time slots in which a channel is set-up or not. hdi : hdlc init hdi = 1, tsa memory, tx hdlc, tx dma, rx hdlc, rx dma and gci controllers are reset within 250ms. an automate writes data from time slot assigner data register (tadr) (except ch0/4 bits) into each tsa memory location. if the microprocessor reads time slot assigner memory after hdlc init, ch0/4 bits of time slot assigner data register are identical to ts0/4 bits of time slot assigner address register. hdi = 0, normal state. n.b. after software reset (bit 2 of idcr register) or pin reset the automate above-mentioned is working. the automate is stopped when the microprocessor writes taar register with hdi = 0. viii - internal registers (continued) STLC5464 61/83
viii.12 - time slot assigner data register - tadr (16)h bit15 bit8 bit7 bit 0 v11 v10 v9 v8 v7 v6 v5 v4 v3 v2 v1 ch4 ch3 ch2 ch1 ch0 after reset (0000) h ch0/4 : channel0/4 these five bits define one of 32 channels associated to time slot defined by the previous register (taar). v1/8 : validation the logical channel chx is constituted by each subchannel 1 to 8 and validated by v1/8 bit v9 : validation subchannel v 9 = 1, each v1/8 bit is taken into account once every 250ms. in transmit direction, data is transmitted consecutively during the time slot of the current frame and during the same time slot of the next frame.id est.: the same data is transmitted in two consecutive frames. in receive direction, hdlc controller fetches data during the time slot of the current frame and ignores data during the same time slot of the next frame. v 9 = 0, each v1/8 bit is taken into account once every 125ms. v10 : direct mhdlc access if v10 = 1, the rx hdlc controller receives data issued from din8 input during the current time slot (bits validated by v1/8) and dout6 output transmits data issued from the tx hdlc controller. if v10 = 0, the rx hdlc controller receives data issued from the matrix output 7 during the current time slot ; dout6 output delivers data issued from the matrix output 6 during the same current time slot. n.b : if d7 = 1, (see ogeneral configuration register gcr (02)ho) the tx hdlc controller is connected to matrix input 7 continuously so the hdlc frames can be sent to any dout (i.e. dout0 to dout7). v11 : validation of cb pin this bit is not taken into account if csma = 1 (hdlc transmit command register). if csma = 0 : v11 = 1, contention bus pin is validated and echo pin (which is an input) is not taken into account. v11 = 0, contention bus pin is high impedance during the current time slot (this pin is an open drain output). viii.13 - hdlc transmit command register - htcr (18)h bit15 bit8 bit7 bit 0 ch4 ch3 ch2 ch1 ch0 read nu cf pen csma ncrc f p1 p0 c1 c0 after reset (0000) h read : read command memory read = 1, read command memory. read = 0, write command memory. ch0/4 : these five bits define one of 32 channels. viii - internal registers (continued) STLC5464 62/83
c1/c0 : command bits c1 c0 commands bits 0 0 abort ; if this command occurs during the current frame, hdlc controller transmits seven o1o immediately, afterwards hdlc controller transmits o1o or flag in accordance with f bit, generates an interrupt and waits new command such as start orn continue. if this command occurs after transmitting a frame, hdlc controller generates an interrupt and waits a new command such as start or continue. 0 1 start ; tx dma controller is now going to transfer first frame from buffer related to initial descriptor. the initial descriptor address is provided by the initiate block located in external memory. 1 0 continue ; tx dma controller is now going to transfer next frame from buffer related to next descriptor. the next descriptor address is provided by the previous descriptor from which the related frame had been already transmitted. 1 1 halt ; after transmitting frame, hdlc controller transmits o1o or flag in accordance with f bit, generates an interrupt and is waiting new command such as start or continue. p0/1 : protocol bits p1 p0 transmission mode 0 0 hdlc 0 1 transparent mode 1 (per byte) ; the fill character defined in fcr register is taken into account. 1 0 transparent mode 2 (per byte) ; the fill character defined in fcr register is not taken into account. 1 1 reserved f : flag f = 1 ; flags are transmitted between closing flag of currentframe and opening flag of next frame. f = 0 ; o1o are transmitted between closing flag of current frame and opening flag of next frame. ncrc : crc not transmitted ncrc = 1, the crc is not transmitted at the end of the frame. ncr c =0, the crc is transmitted at the end of the frame. csma : carrier sense multiple access with contention resolution csma = 1, cb output and the echo bit are taken into account during this channel transmission by the tx hdlc. csma = 0, cb output and the echo bit are defined by v11 (see o time slot assigner data register tadr (16)ho). pen : csma penalty significant if csma = 1 pen = 1, the penalty value is 1 ; a transmitter which has transmitted a frame correctly will count (pri +1) logic one received from echo pin before transmitting next frame. (pri, priority class 8 or 10 given by the buffer descriptor related to the frame. pen = 0, the penalty value is 2 ; a transmitter which has transmitted a frame correctly will count (pri +2) logic one received from echo pin before transmitting next frame. (pri, priority class 8 or 10 given by the transmit descriptor related to the frame). cf : common flag cf = 1, the closing flag of previous frame and opening flag of next frame are identical if the next frame is ready to be transmitted. cf = 0, the closing flag of previous frame and opening flag of next frame are distinct. viii - internal registers (continued) STLC5464 63/83
viii.14 - hdlc receive command register - hrcr (1a)h bit15 bit8 bit7 bit 0 ch4 ch3 ch2 ch1 ch0 read ar21 ar20 ar11 ar10 crc nu p1 p0 c1 c0 after reset (0000) h read : read command memory read = 1, read command memory. read = 0, write command memory. ch0/4 : these five bits define one of 32 channels. c1/c0 : command c1 c0 commands bits 0 0 abort ; if this command occurs during receiving a current frame, hdlc controller stops the reception, generates an interrupt and waits new command such as start orn continue. if this command occurs after receiving a frame, hdlc controller generates an interrupt and waits a new command such as start or continue. 0 1 start ; rx dma controller is now going to transfer first frame into buffer related to the initial descriptor. the initial descriptor address is provided by the initiate block located in external memory. 1 0 continue ; rx dma controller is now going to transfer next frame into buffer related to next descriptor. the next descriptor address is provided by the previous descriptor from which the related frame had been already received. 1 1 halt ; after receiving frame, hdlc controller stops the reception, generates an interrupt and waits a new command such as start or continue. p0/1 : protocol bits p1 p0 transmission mode 0 0 hdlc 0 1 transparent mode 1 (per byte) ; the fill character defined in fcr register is taken into account. 1 0 transparent mode 2 (per byte) ; the fill character defined in fcr register is not taken into account. 1 1 reserved crc : crc stored in external memory crc = 1, the crc is stored at the end of the frame in external memory. crc = 0, the crc is not stored into external memory. ar10 : address recognition10 ar10 = 1, first byte after opening flag of received frame is compared to af0/7 bits of afrdr. if the first byte received and af0/7 bits are not identical the frame is ignored. ar10 = 0, first byte after opening flag of receivedframe is not compared to af0/7 bits of afrdr register. ar11 : address recognition 11 ar11 = 1, first byte after opening flag of received frame is compared to all o1os.if the first byte received is not all o1os the frame is ignored. ar11 = 0, first byte after opening flag of received frame is not compared to all o1os. ar20 : address recognition 20 ar20 = 1, secondbyte after opening flag of received frame is comparedto af8/15bits of afrdr register. if the second byte received and af8/15 bits are not identical the frame is ignored. ar20 = 0, second byte after opening flag of received frame is not compared to af8/15 bits of afrdr register. viii - internal registers (continued) STLC5464 64/83
ar21 : address recognition 21 ar21 = 1, second byte after opening flag of received frame is compared to all o1os. if the second byte received is not all o1os the frame is ignored. ar21 = 0, second byte after opening flag of received frame is not compared to all o1os. second byte first byte conditions to receive a frame ar21 ar20 ar11 ar10 0 0 0 0 each frame is received without condition. 0 0 0 1 only value of the first received byte must be equal to that of af0/7 bits. 0 0 1 0 only value of the first received byte must be equal to all o1os. 0 0 1 1 the value of the first received byte must be equal either to that of af0/7 or to all o1os. 0 1 0 0 only value of the second received byte must be equal to that of af8/15 bits. 0 1 0 1 the value of the first received byte must be equal to that of af0/7 bits and the value of the second received byte must be equal to that of af8/15 bits. 0 1 1 0 the value of first received byte is must be equal to all o1os and the value of second received byte must be equal to that of af8/15 bits. 0 1 1 1 the value of the first received byte must be equal either to that of af0/7 or to all o1os and the value of the second received byte must be equal to that of af8/15 bits. 1 0 0 0 only the value of the second received byte must be equal to all o1os. 1 0 0 1 the value of the first received byte must be equal to that of af0/7 bits and the value of the second received byte must be equal to all o1os. 1 0 1 0 the value of the first received byte must be equal to all o1os and the value of the second received byte must be equal to o1o also. 1 0 1 1 the value of the first received byte must be equal either to that of af0/7 or to o1o and the value of the second received byte must be equal to all o1os. 1 1 0 0 the value of the second received byte must be equal either to that of af8/15 or to all o1os. 1 1 0 1 the value of the first received byte must be equal to that of af0/7 bits and the value of the second received byte must be equal either to that of af8/15 or to all o1os. 1 1 1 0 the value of the first received byte must be equal to o1o and the value of the second received byte must be equal either to that of af8/15 or to all o1os. 1 1 1 1 the value of the first received byte must be equal either to that of af0/7 or to o1o and the value of the second received byte must be equal either to that of af8/15 or to all o1os. viii.15 - address field recognition address register - afrar (1c)h bit15 bit8 bit7 bit 0 ch4 ch3 ch2 ch1 cho read nu nu r e s e r v e d after reset (0000) h the write operation is lauched when afrar is written by the microprocessor. read : read address field recognition memory read=1, read afr memory. read=0, write afr memory. ch0/4 : these five bits define one of 32 channels in reception viii - internal registers (continued) STLC5464 65/83
viii.16 - address field recognition data register - afrdr (1e)h bit15 bit8 bit7 bit 0 af15 af14 af13 af12 af11 af10 af9 af8 af7 af6 af5 af4 af3 af2 af1 af0 after reset (0001) h af0/15 : address field bits af0/7 ; first byte received; af8/15: second byte received. these two bytes are stored into address field recognition memory when afrar is written by the microprocessor. viii.17 - fill character register - fcr (20)h bit15 bit8 bit7 bit 0 r e s e r v e d fc7 fc6 fc5 fc4 fc3 fc2 fc1 fc0 after reset (0000) h fc0/7 : fill character (eight bits) in transparentmode m1, twomessages are separatedby fillcharacters andthe detection of one fill character marks the end of a message. viii.18 - gci channels definition register 0 - gcir0 (22)h the definitions of x and y indices are the same for gcir0, gcir1, gcir2, gcir3 : -0 x 7, 1 of 8 gci channels belonging to the same multiplex tdm4 or tdm5 - y = 0, tdm4 is selected - y = 1, tdm5 is selected. bit15 bit8 bit7 bit 0 ana11 vci11 v*11 vm11 ana10 vci10 v*10 vm10 ana01 vci01 v*01 vm01 ana00 vci00 v*00 vm00 tdm5 tdm4 tdm5 tdm4 gci channel 1 gci channel 0 after reset (0000) h vmxy : validation of monitor channelx, multiplex y : when this bit is at 1, monitor channel xy is validated. when this bit is at 0, monitor channel xy is not validated. on line to reset (if necessary)one mon channel which had been selected previously vmxy must be put at 0 during 125ms before reselecting this channel. deselecting one mon channel during 125ms resets this mon channel. v*xy : validation of v starx, multiplex y when this bit is at 1, v star protocol is validated if vmxy=1. when this bit is at 0, gci monitor protocol is validated if vmxy=1. vcxy : validation of command/indicate channel x, multiplexy when this bit is at 1, command/indicate channelxy is validated. when this bit is at 0, command/indicate channelxy is not validated. it is necessary to let vcxy at o0o during 125ms to initiate the command/indicate channel. anaxy : analog application when this bit is at 1, primitive has 6 bits if c/ixy is validated. when this bit is at 0, primitive has 4 bits if c/ixy is validated. viii - internal registers (continued) STLC5464 66/83
viii.19 - gci channels definition register 1 - gcir1 (24)h bit15 bit8 bit7 bit 0 ana31 vci31 v*31 vm31 ana30 vci30 v*30 vm30 ana21 vci21 v*21 vm21 ana20 vci20 v*20 vm20 tdm5 tdm4 tdm5 tdm4 gci channel 3 gci channel 2 after reset (0000) h for definition see gci channels definition register above. viii.20 - gci channels definition register 2 - gcir2 (26)h bit15 bit8 bit7 bit 0 ana51 vci51 v*51 vm51 ana50 vci50 v*50 vm30 ana41 vci41 v*41 vm41 ana40 vci40 v*40 vm40 tdm5 tdm4 tdm5 tdm4 gci channel 5 gci channel 4 after reset (0000) h for definition see gci channels definition register above. viii.21 - gci channels definition register 3 - gcir3 (28)h bit15 bit8 bit7 bit 0 ana71 vci71 v*71 vm71 ana70 vci70 v*70 vm70 ana61 vci61 v*61 vm61 ana60 vci60 v*60 vm60 tdm5 tdm4 tdm5 tdm4 gci channel 7 gci channel 6 after reset (0000) h for definition see gci channels definition register above. viii - internal registers (continued) STLC5464 67/83
viii.22 - transmit command / indicate register - tcir (2a)h bit15 bit8 bit7 bit 0 0 g0 ca2 ca1 ca0 read 0 0 nu nu c6 c5 c4 c3 c2 c1 after reset (00ff) h when this register is written by the microprocessor, these different bits mean : read : read c/i memory read = 1, read c/i memory. read = 0, write c/i memory. ca 0/2 : transmit command/indicate memory address ca 0/2 : these bits define one of eight command/indicate channels. g0 : this bit defines one of two gci multiplexes. g0 = 0, tdm4 is selected. g0 = 1, tdm5 is selected. c6/1 : new primitive to be transmitted c6 is transmitted first if ana = 1. c4 is transmitted first if ana = 0. the new primitive is taken into account by the transmitter after writing bits 8 to 15 (if 8 bit microprocessor). transmit command/indicate register (after reading) bit15 bit8 bit7 bit 0 0 g0 ca2 ca1 ca0 read nu nu pt1 pt0 c6 c5 c4 c3 c2 c1 when this register is read by the microprocessor, these different bits mean : read : read c/i memory read = 1, read c/i memory. read = 0, write c/i memory. ca 0/2 : transmit c/i address ca 0/2 : these bits define one of eight command/indicate channels. g0 : this bit defines one of two gci multiplexes. g0 = 0, tdm4 is selected. g0 = 1, tdm5 is selected. c6/1 : last primitive transmitted. pt0/1 : status bits p1 p0 primitive status 0 0 primitive has not been transmitted yet. 0 1 primitive has been transmitted once. 1 0 primitive has been transmitted twice. 1 1 primitive has been transmitted three times or more. viii - internal registers (continued) STLC5464 68/83
viii.23 - transmit monitor address register - tmar (2c)h bit15 bit8 bit7 bit 0 0 g0 ma2 ma1 ma0 read nu nu nu nu tiv fabt l nob 0 nu after reset (000f) h when this register is written by the microprocessor, these different bits mean : read : read mon memory read=1, read mon memory. read=0, write mon memory. ma 0/2 : transmit monitor address ma 0/2 :these bits define one of eight monitor channel if validated. g0 : this bit defines one of two gci multiplexes. g0 = 0, tdm4 is selected. g0 = 1, tdm5 is selected. nob : number of byte to be transmitted nob = 1, one byte to transmit. nob = 0, two bytes to transmit. l : last byte l = 1, the word (or the byte) located in the transmit monitor data register (tmdr) is the last. l = 0, the word (or the byte) located in the transmit monitor data register (tmdr) is not the last. fabt : fabt = 1, the current message is aborted by the transmitter. tiv : timer interrupt is validated tiv = 1, time out alarm generates an interrupt when the timer has expired. tiv = 0, time out alarm is masked. if 8 bit microprocessor the data (tmdr register) is taken into account by the transmitter after writing bits 8 to 15 of this register. transmit monitor address register (after reading) bit15 bit8 bit7 bit 0 0 g0 ma2 ma1 ma0 read nu nu nu nu to abt l nobt exe idle when this register is read by the microprocessor, these different bits mean : read, ma0/2, g0 have same definition as already described for the write register cycle. idle : when this bit is at o1o, idle (all 1's) is transmitted during the channel validation. exe : executed when this status bit is at o1o, the command written previously by the microprocessor has been executed and a new word can be stored in the transmit monitor data register (tmdr) by the microprocessor. when this bit is at o0o, the command written previously by the microprocessor has not yet been executed. nobt : number of byte which has been transmitted. nobt = 1, the first byte is transmitting. nob t = 0, the second byte is transmitting, the first byte has been transmitted. l : last byte ; this l bit is the l bit which has been written by the microprocessor. abt : abort abt=1, the remote receiver has aborted the current message. to : time out one millisecond to = 1, the remote receiver has not acknowledged the byte which has been transmitted one millisecond ago. viii - internal registers (continued) STLC5464 69/83
viii.24 - transmit monitor data register - tmdr (2e)h bit15 bit8 bit7 bit 0 m18 m17 m16 m15 m14 m13 m12 m11 m08 m07 m06 m05 m04 m03 m02 m01 after reset (ffff) h m08/01 : first monitor byte to transmit. m08 bit is transmitted first. m18/11 : second monitor byte to transmit if nob = 0 (bit of tmar). m18 bit is transmitted first. viii.25 - transmit monitor interrupt register - tmir (30)h bit15 tdm5 bit8 bit7 tdm4 bit 0 mi71 mi61 mi51 mi41 mi31 mi21 mi11 mi01 mi70 mi60 mi50 mi40 mi30 mi20 mi10 mi00 after reset (0000) h when the microprocessor read this register, this register is reset (0000)h. mixy : transmit monitor channel x interrupt, multiplex y with : 0 x 7, 1 of 8 gci channels belonging to the same multiplex tdm4 or tdm5 y = 0, gci channel belongs to the multiplex tdm4 and y = 1 to tdm5. mixy = 1 when : - a word has been transmitted and pre-acknowledged by the transmit monitor channel xy (in this case the transmit monitor data register (tmdr) is available to transmit a new word) or - the message has been aborted by the remote receive monitor channel or - the timer has reached one millisecond (in accordancewith tiv bit of tmar) by im3 bit of imr. when mixy goes to o1o, the interrupt mtx bit of ir is generated. interrupt mtx can be masked. viii.26 - memory interface configuration register - micr (32)h bit15 bit8 bit7 bit 0 p41 p40 p31 p30 p21 p20 p11 p10 z w v u t s r ref after reset (e400) h ref : memory refresh ref = 1, dram refresh is validated, ref = 0, dram refresh is not validated. r,s,t : these three bits define the external ram circuit organization (1word=2bytes) the cycle duration is always 15.625ms (512 periods of the clock applied on xtal1 pin). tsr if refresh 0 0 0 128k x 8 sram circuit (up to 512k words) 0 0 1 512k x 8 sram circuit (up to 512k words) 0 1 0 256k x 16 dram circuit (up to 1m word) 512 cycles / 8ms 0 1 1 1m x 4 (or 16) bits dram circuit (up to 4m words) 1024 cycles / 16ms 1 0 0 4m x 4 (or 16) bits dram circuit (up to 8m words) 2048 cycles / 32ms 1 0 1 101 to 111 not used (this writting is forbidden) the cycle duration is always 15.625ms (512 periods of the clock applied on xtal1 pin). viii - internal registers (continued) STLC5464 70/83
u,v,w,z : these four bits define the different signals delivered by the mhdlc. first case : the external ram circuit is dram (t = 1 or s = 1) - u defines the time tu comprised between beginning of cycle and falling edge of nras : u = 1, tu = 60ns - u = 0, tu = 30ns - v defines the time tv comprised between falling edge of nras and falling edge of ncas : v = 1, tv = 60ns - v = 0, tv = 30ns - w defines the time tw comprised between falling edge of ncas and rising edge of ncas : w = 1, tw = 60ns - w = 0, tw = 30ns - z defines the time tz comprised between rising edge of ncas and end of cycle : z = 1, tz = 60ns - z = 0, tz = 30ns the total cycle is tu + tv + tw + tz. the different output signals are high impedance during 15ns before the end of each cycle. second case : the external ram circuit is sram (t = 0 or s = 0) - u and v define a part of write cycle for sram : the time tuv comprised between falling edge and rising edge of nce. the total of write cycle is : 15ns+tuv + 15ns. v u tuv 0 0 30ns 0 1 60ns 1 0 90ns 1 1 120ns - w and z define a part of read cycle for sram : the time twz comprised between falling edge of noe and rising edge of noe. the total of read cycle is : twz +30ns z w twz 0 0 30ns 0 1 60ns 1 0 90ns 1 1 120ns n.b. the different output signals are high impedance during 15ns before the end of each cycle. on the outside of each (dram or sram) cycle all the outputs are high impedance or not in accordance with mbl bit (see ombl : memory bus low impedanceo). memory bit15 bit8 bit7 bit 0 p4e1 p4e0 p3e1 p3e0 p2e1 p2e0 p1e1 p1e0 z w v u t s r ref after reset (e400) h p1 e0/1 : priority 1 for entity defined by e0/1 p2 e0/1 : priority 2 for entity defined by e0/1 p3 e0/1 : priority 3 for entity defined by e0/1 p4 e0/1 : priority 4 for entity defined by e0/1 entity definition : e1 e0 entity 0 0 rx dma controller 0 1 microprocessor 1 0 tx dma controller 1 1 interrupt controller viii - internal registers (continued) STLC5464 71/83
priority 5 is the last priority for dram refresh if validated. dram refresh obtains priority 0 (the first priority) automatically when the first half cycle is spend without access to memory. after reset (e400) h , the rx dma controller has the priority 1 the microprocessor has the priority 2 the tx dma controller has the priority 3 the interrupt controller has the priority 4 the dram refresh has the priority 5 viii.27 - initiate block address register - ibar (34)h bit15 bit8 bit7 bit 0 a23 a22 a21 a20 a19 a18 a17 a16 a15 a14 a13 a12 a11 a10 a9 a8 after reset (0000)h a8/23 : address bits. these 16 bits are the segment address bits of the initiate block (a8 to a23 for the external memory).the offset is zero (a0 to a7 =o0o). the initiate block address (iba) is : 23 87 0 a23a22a21a20a19a18a17a16a15a14a13a12a11a10a9a800000000 the 23 more significant bits define one of 8 megawords. (one word comprises two bytes.) the least significant bit defines one of two bytes when the microprocessor selects one byte. viii.28 - interrupt queue size register - iqsr (36)h bit15 bit8 bit7 bit 0 r e s e r v e d hs2 hs1 hs0 ms2 ms1 ms0 cs1 cs0 after reset (0000) h cs0/1 : command/indicate interrupt queue size these two bits define the size of command/indicate interrupt queue in external memory. the location is iba + 256 + hdlc queue size + monitor channel queue size (see the initiate block address (iba)). ms0/2 : monitor channel interrupt queue size these three bits define the size of monitor channel interrupt queue in external memory. the location is iba + 256 + hdlc queue size. hs0/2 : hdlc interrupt queue size these three bits define the size of hdlc status interrupt queue in external memory for each channel. the location is iba+256 (see the initiate block address (iba)) hs2 hs1 hs0 hdlc queue size ms2 ms1 ms0 mon queue size cs1 cs0 c/i queue size 0 0 0 128 words 0 0 0 128 words 0 0 64 words 0 0 1 256 words 0 0 1 256 words 0 1 128 words 0 1 0 384 words 0 1 0 384 words 1 0 192 words 0 1 1 512 words 0 1 1 512 words 1 1 256 words 1 0 0 640 words 1 0 0 640 words 1 0 1 768 words 1 0 1 768 words 1 1 0 896 words 1 1 0 896 words 1 1 1 1024 words 1 1 1 1024 words viii - internal registers (continued) STLC5464 72/83
viii.29 - interrupt register - ir (38)h bit15 bit8 bit7 bit 0 nu nu sfco prsr tim int fov int fwar tx fov tx fwar rx fov rx fwar icov mtx mrx c/irx hdlc after reset (0000) h this register is read only. when this register is read by the microprocessor, this register is reset (0000) h . if not masked, each bit at o1o generates o1o on int0 pin. hdlc : hdlc interrupt hdlc = 1, tx hdlc or rx hdlc has generated an interrupt the status is in the hdlc queue. c/irx : command/indicate rx interrupt c/irx = 1, rx commande/indicate has generated an interrupt. the status is in the hdlc queue. mrx : rx monitor channel interrupt mrx = 1, one rx monitor channel has generated an interrupt.the status is in the rx monitor channel queue. mtx : tx monitor channel interrupt mtx = 1, one or several tx monitor channels have generated an interrupt. transmit monitor interrupt register (tmir) indicates the tx monitor channels which have generated this interrupt. icov : interrupt circular overload icov = 1, one of three circular interrupt memories is completed. rxfwar : rx dma controller fifo warning rxfwar = 1, rx dma controller has generated an interrupt, its fifo is 3/4 completed. rxfov : rx dma controller fifo overload rxfov = 1, rx dma controller has generatedan interrupt, it cannottransfer data from rx hdlc to external memory, its fifo is completed. txfwar : tx dma controller fifo warning txfwar = 1, tx dma controller has generated an interrupt, its fifo is 3/4 completed. txfov : tx dma controller fifo overload txfov = 1, tx dmacontroller has generated an interrupt, it cannot transfer data from tx hdlc to external memory, its fifo is completed. intfwar : interrupt controller fifo warning intfwar = 1, interrupt controller has generated an interrupt, its fifo is 3/4 completed. intfov : interrupt controller fifo overload intfov = 1, interrupt controller has generated an interrupt, it cannot transfer status from dma and gci controllers to external memory, its internal fifo is completed. tim : timer tim = 1, the programmable timer has generated an interrupt. prsr : pseudo random sequence recovered prsr = 1,the pseudo random sequencetransmitted by the generatorhas been recovered by the analyzer. sfco : sequence fault counter overload sfco = 1, the fault counter has reached the value ffff(h). viii - internal registers (continued) STLC5464 73/83
viii.30 - interrupt mask register - imr (3a)h bit15 bit8 bit7 bit 0 nu nu im13 im12 im11 im10 im9 im8 im7 im6 im5 im4 im3 im2 im1 im0 after reset (ffff) h im13/0 : interrupt mask 0/7 when im0 = 1, hdlc bit is masked. when im1 =1, c/irx bit is masked. when im2 = 1, mrx bit is masked. when im3 = 1, mtx bit is masked. when im4 = 1, icov bit is masked when im5 = 1, rxfwar bit is masked. when im6 = 1, rxfov bit is masked. when im7 = 1, txfwar bit is masked. when im8 = 1, txfov bit is masked. when im9 = 1, intfwar bit is masked. when im10 = 1, intfov bit is masked. when im11 = 1, tim bit is masked. when im12 = 1, prsr bit is masked. when im13 = 1, sfco bit is masked. viii.31 - time register - timr (3c)h bit15 bit8 bit7 bit 0 s3 s2 s1 s0 ms9 ms8 ms7 ms6 ms5 ms4 ms3 ms2 ms1 ms0 mm1 mm0 0 to 5s 0 to 999ms 0 to 3x0.25ms after reset (0800) h id 512ms this programmable register indicates the time at the end of which the watch dog delivers logic o1o on the pin wdo (which is an output) but only if the microprocessor does not reset the counter assigned (with the help of wdr bit of idcr identification and dynamic command register) during the time defined by the timer register. the timer register and its counter can be used as a time base by the microprocessor. an interrupt (tim) is generated at each period defined by the timer register if the microprocessor does not reset the counter with the help of wdr (bit of idcr). when tsv=1{time stamping validated (gcr)} this programmable register is not used. viii.32 - test register - tr (3e)h bit15 bit8 bit7 bit 0 t15/0 : test bits 0/15 these bits are reserved for the test of the circuit in production viii - internal registers (continued) STLC5464 74/83
ix - external registers these registers are located in shared memory. initiate block address register (ibar) gives the initiate block address (iba) in shared memory (see register ibar(34)h on page 73). `not used' bits (nu) are accessible by the microprocessor but the use of these bits by software is not recommended. ix.1 - initialization block in external memory descriptor address channel address bit15 bit8 bit7 bit0 ch 0 t iba+00 not used tda high iba+02 transmit descriptor address (tda low) r iba+04 not used rda high iba+06 receive descriptor address (rda low) ch1 t iba+08 not used tda high iba+10 transmit descriptor address (tda low) r iba+12 not used rda high iba+14 receive descriptor address (rda low) ch 2 to ch30 iba+16 to iba+246 ch 31 t iba+248 not used tda high iba+250 transmit descriptor address (tda low) r iba+252 not used rda high iba+254 receive descriptor address (rda low) when direct memory access controller receives start from one of 64 channels, it reads initialization block immediately to know the first address of the first descriptor for this channel. bit 0 of transmit descriptor address (tda low) and bit 0 of receive descriptor address (rda low), are at zero mandatory. this least significant bit is not used by dma controller, the shared memory is always a 16 bit memory for the dma controller. n.b. if several descriptors are used to transmit one frame then before transmitting frame, dma controller stores the address of the first transmit descriptor address into this initialization block. STLC5464 75/83
ix.2 - receive descriptor this receive descriptor is located in shared memory. the quantity of descriptors is limited by the memory size only. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rda+00 ibc eoq size of the buffer (sob) 0 rda+02 not used rba high (8 bits) rda+04 receive buffer address low (16 bits) rda+06 not used nrda high (8 bits) rda+08 next receive descriptor address low (16 bits) rda+10 fr abt ovf fcrc number of bytes received (nbr) the 5 first words located in shared memory to rda+00 from rda+08 are written by the microprocessor and read by the dmac only. the 6th word located in shared memory in rda+10 is written by the dmac only during the frame reception and read by the microprocessor. sob : size of the buffer associated to descriptor up to 2048 words (1 word = 2 bytes). if sob = 0, dmac goes to next descriptor. rba : receive buffer address. lsb of rba low is at zero mandatory. rda : receive descriptor address. nrda : next receive descriptor address. lsb of nrda low is at zero mandatory. nbr : number of bytes received (up to 4096). ix.2.1 - bits written by the microprocessor only ibc : interrupt if the buffer has been completed. ibc=1, the dmac generates an interrupt if the buffer has been completed. eoq : end of queue. eoq=1, the dmac stops immediately its reception generates an interrupt (hdlc = 1 in ir) and waits a command from the hrcr (hdlc receive command register). eoq=0, the dmac continues. ix.2.2 - bits written by the rx dmac only fr abt ovf fcrc definition 1 0 0 0 the frame has been received without error. the end of frame is in this buffer. 1 0 0 1 the frame has been received with false crc. 0 0 0 0 if nbr is different to 0, the buffer related to this descriptor is completed.the end of frame is not in this buffer. 0 0 0 0 if nbr is equal to 0, the rx dmac is receiving a frame. 0 1 0 0 abort. the received frame has been aborted by the remote transmitter or the local microprocessor. 0 1 1 0 overflow of fifo. the received frame has been aborted. 0 1 0 1 the received frame had not an integer of bytes. ix.2.3 - receive buffer each receive buffer is defined by its receive descriptor. the maximum size of the buffer is 2048 words (1 word=2 bytes) 15 0 rba first buffer location rba + sob-2 last location available = recive buffer address (rba) + size of the buffer (sob-2) ix - external registers (continued) STLC5464 76/83
ix.3 - transmit descriptor this transmit descriptor is located in shared memory. the quantity of descriptors is limited by the memory size only. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 tda+00 bint bof eof eoq number of bytes to be transmitted (nbt) tda+02 not used crc c pri tba high (8 bits) tda+04 transmit buffer address low (16 bits) tda+06 not used ntda high (8 bits) tda+08 next transmit descriptor address low (16 bits) tda+10 cft abt und the 5 first words located in shared memory to tda+00 from tda+08 are written by the microprocessor and read by the dmac only. the 6th word located in shared memory in tda+10 is written by the dmac only during the frame reception and read by the microprocessor. nbt : number of bytes to be transmitted (up to 4096). tba : transmit buffer address. lsb of tba low is at zero mandatory. tda : transmit descriptor address. ntda : next transmit descriptor address. lsb of ntda low is at zero mandatory. ix.3.1 - bits written by the microprocessor only bint : interrupt at the end of the frame or when the buffer is become empty. bint = 1, if eof = 1 the dmac generates an interrupt when the frame has been transmitted ; if eof = 0 the dmac generates an interrupt when the buffer is become empty. bint = 0, the dmac does not generate an interrupt during the transmission of the frame. bof : beginning of frame bof = 1,the transmit bufferassociated to this transmit descriptor containsthe beginning of frame. bof = 0,the transmit buffer associated to this transmitdescriptor does not contain the beginning of frame. eof : end of frame eof = 1,the transmit buffer associated to this transmit descriptor contains the end of frame. eof = 0,the transmit buffer associated to this transmit descriptor does not contain the end of frame. eoq : end of queue eoq = 1, the dmac stops immediately its transmission, generates an interrupt (hdlc = 1 in ir) and waits a command from the htcr (hdlc transmit command register). eoq = 0, the dmac continues. crcc : crc corrupted crcc = 1,at the end of this frame the crc will be corrupted by the tx hdlc controller. pri : priority class 8 or 10 pri = 1, if csma/cr is validated for this channel, the priority class is 8. pri = 0, if csma/cr is validated for this channel the priority class is 10. (see register csma) ix - external registers (continued) STLC5464 77/83
ix.3.2 - bits written by the rx dmac only cft : frame correctly transmitted cft = 1, the frame has been correctly transmitted. cft = 0, the frame has not been correctly transmitted. abt : frame transmitting aborted abt = 1, the frame has been aborted by the microprocessor during the transmission. abt = 0, the microprocessor has not aborted the frame during the transmission. und : underrun und = 1, the transmit fifo has not been fed correctly during the transmission. und = 0, the transmit fifo has been fed correctly during the transmission. ix.3.3 - transmit buffer each transmit buffer is defined by its transmit descriptor. the maximum size of the buffer is 2048 words (1 word=2 bytes) 15 0 tba first word to transmit tba + x ; nbt is odd : x = nbt - 1 nbt is even : x = nbt - 2 last word to transmit ix.4 - receive & transmit hdlc frame interrupt bit15 bit8 bit7 bit 0 ns 0 tx a4 a3 a2 a1 a0 0 0 0 cft/cfr be/bf halt eoq rrlf/erf this word is located in the hdlc interrupt queue ; iqsr register indicates the size of this hdlc interrupt queue located in the external memory. ns : new status. before writing the features of event in the external memory the interrupt controller reads the ns bit : if ns = 0, the interrupt controller puts this bit at `1' when it writes the status word of the frame which has been transmitted or received. if ns = 1, the interrupt controller puts icov bit at `1' to generate an interrupt (ir register). when the microprocessor has read the status word, it puts this bit at `0' to acknowledge the new status. this location becomes free for the interrupt controller. transmitter tx : tx = 1, transmitter a4/0 : tx hdlc channel 0 to 31 rrlf : ready to repeat last frame in consequenceof event suchas abort command hdlc, controller is waiting start or continue. eoq : end of queue the transmit dma controller (or the receive dma controller) has encountered the current descriptor with eoq at o1o. dma controller is waiting ocontinueo from microprocessor. halt : the transmitdmacontroller hasreceivedhalt from the microprocessor; it is waitingocontinueo from microprocessor. be : buffer empty if bint bit of transmit descriptor is at `1', the transmit dma controller puts be at o1o when the buffer has been emptied. cft : correctly frame transmitted a frame has been transmitted. this status is provided only if bint bit of transmit descriptor is at `1'. cft is located in the last descriptor if several descriptors are used to define a frame. ix - external registers (continued) STLC5464 78/83
receiver tx : tx = 0, receiver a4/0 : rx hdlc channel 0 to 31 erf : error detected on received frame an error such as crc not correct, abort, overflow has been detected. eoq : end of queue the receive dma controller has encountered the current receive descriptor with eoq at o1o. dma controller is waiting ocontinueo from microprocessor. halt : the receive dma controller has received halt or abort (on the outside of frame) from the microprocessor; it is waiting ocontinueo from the microprocessor. be : buffer filled if ibc bit of receiver descriptor is at `1', the receive dma controller puts bf ato1o when it has filled the current buffer with data from the received frame. cfr : correctly frame received a receive frame is ended with a correct crc. the end ofthe frame islocated in the last descriptor if several descriptors. ix.5 - receive command / indicate interrupt ix.5.1 - receive command / indicate interrupt when tsv = 0 time stamping not validated (bit of gcr register) bit15 bit8 bit7 bit 0 ns nu nu nu g0 a2 a1 a0 nu nu c6 c5 c4 c3 c2 c1 this word is located in the command/indicate interrupt queue ; iqsr register indicates the size of this interrupt queue located in the external memory. ns : new status. before writing the features of event in the external memory the interrupt controller reads the ns bit : if ns = 0, the interrupt controller puts this bit at `1' when it writes the new primitive which has been received. if ns = 1, the interrupt controller puts icov bit at `1' to generate an interrupt (ir register). when the microprocessor has read the status word, it puts this bit at `0' to acknowledge the new status. this location becomes free for the interrupt controller. g0 : g0 = 0, gci 0 corresponding to din4 input and dout4 output. g0 = 1, gci 1 corresponding to din5 input and dout5 output. a2/0 : command/indicate channel 0 to 7 being owned by gci 0 or gci 1 c6/1 : new primitive received twice consecutively ix - external registers (continued) STLC5464 79/83
ix.5.2 - receive command / indicate interrupt when tsv = 1 time stamping validated (bit of gcr register) bit15 bit8 bit7 bit 0 ns nu nu nu g0 a2 a1 a0 nu nu c6 c5 c4 c3 c2 c1 t15t14t13t12t11t10t9t8t7t6t5t4t3t2t1t0 these two words are located in the command/indicate interrupt queue ; iqsr register indicates the size of this interrupt queue located in the external memory. ns : new status. before writing the features of event in the external memory the interrupt controller reads the ns bit : if ns = 0, the interrupt controller puts this bit at `1' when it writes the new primitive which has been received. if ns = 1, the interrupt controller puts icov bit at `1' to generate an interrupt (ir register). when the microprocessor has read the status word, it puts this bit at `0' to acknowledge the new status. this location becomes free for the interrupt controller. g0 : g0 = 0, gci 0 corresponding to din4 input and dout4 output. g0 = 1, gci 1 corresponding to din5 input and dout5 output. a2/0 : command/indicate channel 0 to 7 being owned by gci 0 or gci 1 c6/1 : new primitive received twice consecutively t15/0 : binary counter value when a new primitive is occurred. ix.6 - receive monitor interrupt ix.6.1 - receive monitor interrupt when tsv = 0 tsv : time stamping not validated (bit of gcr register) bit15 bit8 bit7 bit 0 ns g0 a2 a1 a0 odd a f l m18 m17 m16 m15 m14 m13 m12 m11 m8 m7 m6 m5 m4 m3 m2 m1 these two words are transferred into the monitor interrupt queue ; iqsr register indicates the size of this interrupt queue located in the external memory. ns : new status. before writing the features of event in the external memory the interrupt controller reads the ns bit : if ns = 0, the interrupt controller stores two new bytes m1/8 and m11/18 then puts ns bit at `1' when it writes the status of these two bytes which has been received. if ns = 1, the interrupt controller puts icov bit at `1' to generate an interrupt (ir register). g0 : g0 = 0, gci 0 corresponding to din4 input and dout4 output. g0 = 1, gci 1 corresponding to din5 input and dout5 output. l : last byte l = 1, the following word containsthe last byte of messageif odd =1, the previous word contains the last byte of message if odd = 0. l = 0, the following word and the previous word does not contains the last byte of message. f : first byte f=1, the following word contains the first byte of message. f=0, the following word does not contain the first byte of message. a : abort a=1, received message has been aborted. ix - external registers (continued) STLC5464 80/83
odd : odd byte number odd = 1, one byte has been written in the following word. odd = 0, two bytes have been written in the following word. in case of v* protocol odd,a,f,l bits are respectively 1,0,1,1. m1/8 : new byte received twice consecutively if gci protocol has been validated. byte received once if v* protocol has been validated. m11/18 : next new byte received twice consecutively if gci protocol has been validated. this byte is at o1o in case of v* protocol. ix.6.2 - receive monitor interrupt when tsv = 1 tsv : time stamping validated (bit of gcr register) bit15 bit8 bit7 bit 0 ns g0 a2 a1 a0 odd a f l m18 m17 m16 m15 m14 m13 m12 m11 m8 m7 m6 m5 m4 m3 m2 m1 t15t14t13t12t11t10t9t8t7t6t5t4t3t2t1t0 0000000000000000 these four words are located in the monitor interrupt queue ; iqsr register indicates the size of this interrupt queue located in the external memory. ns : new status. before writing the features of event in the external memory the interrupt controller reads the ns bit : if ns = 0, the interrupt controller stores two new bytes m1/8 and m11/18 then puts ns bit at `1' when it writes the status of these two bytes which has been received. if ns = 1, the interrupt controller puts icov bit at `1' to generate an interrupt (ir register). g0 : g0 = 0, gci 0 corresponding to din4 input and dout4 output. g0 = 1, gci 1 corresponding to din5 input and dout5 output. l : last byte l = 1, the following word contains the last byte of message. l = 0, the last byte of message is not the following word. f : first byte f=1, the following word contains the first byte of message. f=0, the first byte of message is not the following word. a : abort a=1, received message has been aborted. odd : odd byte number odd = 1, one byte has been written in the following word. odd = 0, two bytes have been written in the following word. m1/8 : new byte received twice consecutively if gci protocol has been validated. byte received once if v* protocol has been validated. m11/18 : next new byte received twice consecutively if gci protocol has been validated. this byte is at o1o in case of v* protocol. t15/0 : binary counter value when a new primitive is occurred. ix - external registers (continued) STLC5464 81/83
pmpqf160.eps x - package mechanical data 160 pins - plastic quad flat pack dimensions millimeters inches min. typ. max. min. typ. max. a 4.07 0.160 a1 0.25 0.010 a2 3.17 3.42 3.67 0.125 0.135 0.144 b 0.22 0.38 0.009 0.015 c 0.13 0.23 0.005 0.009 d 30.95 31.20 31.45 1.219 1.228 1.238 d1 27.90 28.00 28.10 1.098 1.102 1.106 d3 25.35 0.998 e 0.65 0.026 e 30.95 31.20 31.45 1.219 1.228 1.238 e1 27.90 28.00 28.10 1.098 1.102 1.106 e3 25.35 0.998 l 0.65 0.80 0.95 0.026 0.0315 0.0374 l1 1.60 0.063 k0 o (min.), 7 o (max.) pqfp 160.tb l STLC5464 82/83
information furni shed is believed to be accurate and reliable. however, sgs-thomson micr oelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no licence is granted by implication or otherwise und erany patent or patent rights of sgs-thomson microelectronics. specifications mentioned in this publication are subject to change without notice. this pu blication supersedes and replaces all information previously supplied. sgs-thomson microelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of sgs-thomson microelectronics. ? 1997 sgs-thomson microelectronics - all rights reserved purchase of i 2 c components of sgs-thomson microelectronics, conveys a license under the philips i 2 c patent. rights to use these components in a i 2 c system, is granted provided that the system conforms to the i 2 c standard specifications as defined by philips. sgs-thomson microelectronics group of companies australia - brazil - canada - china - france - germany - hong kong - italy - japan - korea - malaysia - malta - morocco the netherlands - singapore - spain - sweden - switzerland - taiwan - thailand - united kingdom - u.s.a. STLC5464 83/83

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